From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: <iommu@lists.linux-foundation.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
Chao Hao <chao.hao@mediatek.com>, FY Yang <fy.yang@mediatek.com>,
Yong Wu <yong.wu@mediatek.com>, TH Yang <th.yang@mediatek.com>
Subject: [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Fri, 3 Jul 2020 12:41:22 +0800 [thread overview]
Message-ID: <20200703044127.27438-6-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
For mt6779, MMU_INV_SEL register's offset is changed from
0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
use it.
In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
before mt6779.
Cc: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/iommu/mtk_iommu.c | 9 ++++++---
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 219d7aa6f059..533b8f76f592 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,7 +37,7 @@
#define REG_MMU_INVLD_START_A 0x024
#define REG_MMU_INVLD_END_A 0x028
-#define REG_MMU_INV_SEL 0x038
+#define REG_MMU_INV_SEL_GEN1 0x038
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
@@ -178,7 +178,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
for_each_m4u(data) {
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
wmb(); /* Make sure the tlb flush all done */
}
@@ -195,7 +195,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
for_each_m4u(data) {
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
writel_relaxed(iova + size - 1,
@@ -784,18 +784,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.flags = RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5225a9170aaa..cf53f5e80d22 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
+ u32 inv_sel_reg;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Fri, 3 Jul 2020 12:41:22 +0800 [thread overview]
Message-ID: <20200703044127.27438-6-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
For mt6779, MMU_INV_SEL register's offset is changed from
0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
use it.
In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
before mt6779.
Cc: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/iommu/mtk_iommu.c | 9 ++++++---
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 219d7aa6f059..533b8f76f592 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,7 +37,7 @@
#define REG_MMU_INVLD_START_A 0x024
#define REG_MMU_INVLD_END_A 0x028
-#define REG_MMU_INV_SEL 0x038
+#define REG_MMU_INV_SEL_GEN1 0x038
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
@@ -178,7 +178,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
for_each_m4u(data) {
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
wmb(); /* Make sure the tlb flush all done */
}
@@ -195,7 +195,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
for_each_m4u(data) {
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
writel_relaxed(iova + size - 1,
@@ -784,18 +784,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.flags = RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5225a9170aaa..cf53f5e80d22 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
+ u32 inv_sel_reg;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Fri, 3 Jul 2020 12:41:22 +0800 [thread overview]
Message-ID: <20200703044127.27438-6-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
For mt6779, MMU_INV_SEL register's offset is changed from
0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
use it.
In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
before mt6779.
Cc: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/iommu/mtk_iommu.c | 9 ++++++---
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 219d7aa6f059..533b8f76f592 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,7 +37,7 @@
#define REG_MMU_INVLD_START_A 0x024
#define REG_MMU_INVLD_END_A 0x028
-#define REG_MMU_INV_SEL 0x038
+#define REG_MMU_INV_SEL_GEN1 0x038
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
@@ -178,7 +178,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
for_each_m4u(data) {
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
wmb(); /* Make sure the tlb flush all done */
}
@@ -195,7 +195,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
for_each_m4u(data) {
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
writel_relaxed(iova + size - 1,
@@ -784,18 +784,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.flags = RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5225a9170aaa..cf53f5e80d22 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
+ u32 inv_sel_reg;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Chao Hao <chao.hao@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org, FY Yang <fy.yang@mediatek.com>,
wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org,
Chao Hao <chao.hao@mediatek.com>,
iommu@lists.linux-foundation.org, TH Yang <th.yang@mediatek.com>,
linux-mediatek@lists.infradead.org,
Yong Wu <yong.wu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data
Date: Fri, 3 Jul 2020 12:41:22 +0800 [thread overview]
Message-ID: <20200703044127.27438-6-chao.hao@mediatek.com> (raw)
In-Reply-To: <20200703044127.27438-1-chao.hao@mediatek.com>
For mt6779, MMU_INV_SEL register's offset is changed from
0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to
use it.
In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it
before mt6779.
Cc: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/iommu/mtk_iommu.c | 9 ++++++---
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 219d7aa6f059..533b8f76f592 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,7 +37,7 @@
#define REG_MMU_INVLD_START_A 0x024
#define REG_MMU_INVLD_END_A 0x028
-#define REG_MMU_INV_SEL 0x038
+#define REG_MMU_INV_SEL_GEN1 0x038
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
@@ -178,7 +178,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
for_each_m4u(data) {
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
wmb(); /* Make sure the tlb flush all done */
}
@@ -195,7 +195,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
for_each_m4u(data) {
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
writel_relaxed(iova + size - 1,
@@ -784,18 +784,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
};
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.flags = RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5225a9170aaa..cf53f5e80d22 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ enum mtk_iommu_plat {
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
+ u32 inv_sel_reg;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-03 4:42 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 4:41 [PATCH v6 00/10] MT6779 IOMMU SUPPORT Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-04 1:16 ` Yingjoe Chen
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-06 15:17 ` Matthias Brugger
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-08 10:44 ` chao hao
2020-07-03 4:41 ` [PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-06 15:18 ` Matthias Brugger
2020-07-03 4:41 ` Chao Hao [this message]
2020-07-03 4:41 ` [PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-06 15:20 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-10 13:49 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` [PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-06 15:22 ` Matthias Brugger
2020-07-03 4:41 ` [PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-03 4:41 ` Chao Hao
2020-07-10 14:13 ` [PATCH v6 00/10] MT6779 IOMMU SUPPORT Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-10 14:13 ` Joerg Roedel
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-11 7:11 ` Yong Wu
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
2020-07-13 13:29 ` Joerg Roedel
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