From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>,
linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-acpi@vger.kernel.org
Subject: [PATCH v4 12/16] pwm: crc: Implement get_state() method
Date: Wed, 8 Jul 2020 23:14:28 +0200 [thread overview]
Message-ID: <20200708211432.28612-13-hdegoede@redhat.com> (raw)
In-Reply-To: <20200708211432.28612-1-hdegoede@redhat.com>
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v4:
- Use DIV_ROUND_UP when calculating the period and duty_cycle from the
controller's register values
Changes in v3:
- Add Andy's Reviewed-by tag
- Remove extra whitespace to align some code after assignments (requested by
Uwe Kleine-König)
---
drivers/pwm/pwm-crc.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 8a7f4707279c..e58b0979d708 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -119,8 +119,39 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
+static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
+ struct device *dev = crc_pwm->chip.dev;
+ unsigned int clk_div, clk_div_reg, duty_cycle_reg;
+ int error;
+
+ error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
+ return;
+ }
+
+ error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
+ return;
+ }
+
+ clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
+
+ state->period =
+ DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
+ state->duty_cycle =
+ DIV_ROUND_UP(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
+}
+
static const struct pwm_ops crc_pwm_ops = {
.apply = crc_pwm_apply,
+ .get_state = crc_pwm_get_state,
};
static int crystalcove_pwm_probe(struct platform_device *pdev)
--
2.26.2
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-acpi@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Hans de Goede <hdegoede@redhat.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH v4 12/16] pwm: crc: Implement get_state() method
Date: Wed, 8 Jul 2020 23:14:28 +0200 [thread overview]
Message-ID: <20200708211432.28612-13-hdegoede@redhat.com> (raw)
In-Reply-To: <20200708211432.28612-1-hdegoede@redhat.com>
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v4:
- Use DIV_ROUND_UP when calculating the period and duty_cycle from the
controller's register values
Changes in v3:
- Add Andy's Reviewed-by tag
- Remove extra whitespace to align some code after assignments (requested by
Uwe Kleine-König)
---
drivers/pwm/pwm-crc.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 8a7f4707279c..e58b0979d708 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -119,8 +119,39 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
+static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
+ struct device *dev = crc_pwm->chip.dev;
+ unsigned int clk_div, clk_div_reg, duty_cycle_reg;
+ int error;
+
+ error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
+ return;
+ }
+
+ error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
+ return;
+ }
+
+ clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
+
+ state->period =
+ DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
+ state->duty_cycle =
+ DIV_ROUND_UP(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
+}
+
static const struct pwm_ops crc_pwm_ops = {
.apply = crc_pwm_apply,
+ .get_state = crc_pwm_get_state,
};
static int crystalcove_pwm_probe(struct platform_device *pdev)
--
2.26.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-acpi@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [Intel-gfx] [PATCH v4 12/16] pwm: crc: Implement get_state() method
Date: Wed, 8 Jul 2020 23:14:28 +0200 [thread overview]
Message-ID: <20200708211432.28612-13-hdegoede@redhat.com> (raw)
In-Reply-To: <20200708211432.28612-1-hdegoede@redhat.com>
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v4:
- Use DIV_ROUND_UP when calculating the period and duty_cycle from the
controller's register values
Changes in v3:
- Add Andy's Reviewed-by tag
- Remove extra whitespace to align some code after assignments (requested by
Uwe Kleine-König)
---
drivers/pwm/pwm-crc.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 8a7f4707279c..e58b0979d708 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -119,8 +119,39 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
+static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
+ struct device *dev = crc_pwm->chip.dev;
+ unsigned int clk_div, clk_div_reg, duty_cycle_reg;
+ int error;
+
+ error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
+ return;
+ }
+
+ error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
+ if (error) {
+ dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
+ return;
+ }
+
+ clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
+
+ state->period =
+ DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
+ state->duty_cycle =
+ DIV_ROUND_UP(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
+}
+
static const struct pwm_ops crc_pwm_ops = {
.apply = crc_pwm_apply,
+ .get_state = crc_pwm_get_state,
};
static int crystalcove_pwm_probe(struct platform_device *pdev)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-07-08 21:15 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 21:14 [PATCH v4 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 03/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 04/16] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-09 12:53 ` Andy Shevchenko
2020-07-09 12:53 ` [Intel-gfx] " Andy Shevchenko
2020-07-09 12:53 ` Andy Shevchenko
2020-07-09 13:23 ` Hans de Goede
2020-07-09 13:23 ` [Intel-gfx] " Hans de Goede
2020-07-09 13:23 ` Hans de Goede
2020-07-09 14:21 ` Andy Shevchenko
2020-07-09 14:21 ` [Intel-gfx] " Andy Shevchenko
2020-07-09 14:21 ` Andy Shevchenko
2020-07-09 14:33 ` Hans de Goede
2020-07-09 14:33 ` [Intel-gfx] " Hans de Goede
2020-07-09 14:33 ` Hans de Goede
2020-07-09 14:51 ` Andy Shevchenko
2020-07-09 14:51 ` [Intel-gfx] " Andy Shevchenko
2020-07-09 14:51 ` Andy Shevchenko
2020-07-08 21:14 ` [PATCH v4 05/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-09 13:36 ` Andy Shevchenko
2020-07-09 13:36 ` [Intel-gfx] " Andy Shevchenko
2020-07-09 13:36 ` Andy Shevchenko
2020-07-09 13:48 ` Hans de Goede
2020-07-09 13:48 ` [Intel-gfx] " Hans de Goede
2020-07-09 13:48 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 06/16] pwm: lpss: Correct get_state result for base_unit == 0 Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-09 14:50 ` Andy Shevchenko
2020-07-09 14:50 ` [Intel-gfx] " Andy Shevchenko
2020-07-09 14:50 ` Andy Shevchenko
2020-07-09 15:47 ` Hans de Goede
2020-07-09 15:47 ` [Intel-gfx] " Hans de Goede
2020-07-09 15:47 ` Hans de Goede
2020-07-11 6:11 ` Uwe Kleine-König
2020-07-11 6:11 ` [Intel-gfx] " Uwe Kleine-König
2020-07-11 6:11 ` Uwe Kleine-König
2020-07-11 13:58 ` Hans de Goede
2020-07-11 13:58 ` [Intel-gfx] " Hans de Goede
2020-07-11 13:58 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 09/16] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 10/16] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` Hans de Goede [this message]
2020-07-08 21:14 ` [Intel-gfx] [PATCH v4 12/16] pwm: crc: Implement get_state() method Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 15/16] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-08 21:14 ` [PATCH v4 16/16] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-07-08 21:14 ` [Intel-gfx] " Hans de Goede
2020-07-08 21:14 ` Hans de Goede
2020-07-11 6:32 ` Uwe Kleine-König
2020-07-11 6:32 ` [Intel-gfx] " Uwe Kleine-König
2020-07-11 6:32 ` Uwe Kleine-König
2020-07-11 13:51 ` Hans de Goede
2020-07-11 13:51 ` [Intel-gfx] " Hans de Goede
2020-07-11 13:51 ` Hans de Goede
2020-07-08 22:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API (rev2) Patchwork
2020-07-08 22:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 3:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-09 7:09 ` Hans de Goede
2020-07-09 14:14 ` [PATCH v4 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Sam Ravnborg
2020-07-09 14:14 ` [Intel-gfx] " Sam Ravnborg
2020-07-09 14:14 ` Sam Ravnborg
2020-07-09 14:40 ` Hans de Goede
2020-07-09 14:40 ` [Intel-gfx] " Hans de Goede
2020-07-09 14:40 ` Hans de Goede
2020-07-09 15:23 ` Sam Ravnborg
2020-07-09 15:23 ` [Intel-gfx] " Sam Ravnborg
2020-07-09 15:23 ` Sam Ravnborg
2020-07-11 6:19 ` Uwe Kleine-König
2020-07-11 6:19 ` [Intel-gfx] " Uwe Kleine-König
2020-07-11 6:19 ` Uwe Kleine-König
2020-07-11 13:46 ` Hans de Goede
2020-07-11 13:46 ` [Intel-gfx] " Hans de Goede
2020-07-11 13:46 ` Hans de Goede
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