From: Joerg Roedel <joro@8bytes.org>
To: Ashok Raj <ashok.raj@intel.com>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lu Baolu <baolu.lu@intel.com>,
stable@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org
Subject: Re: [PATCH v3 1/1] PCI/ATS: Check PRI supported on the PF device when SRIOV is enabled
Date: Fri, 24 Jul 2020 10:48:59 +0200 [thread overview]
Message-ID: <20200724084859.GQ27672@8bytes.org> (raw)
In-Reply-To: <1595543849-19692-1-git-send-email-ashok.raj@intel.com>
On Thu, Jul 23, 2020 at 03:37:29PM -0700, Ashok Raj wrote:
> PASID and PRI capabilities are only enumerated in PF devices. VF devices
> do not enumerate these capabilites. IOMMU drivers also need to enumerate
> them before enabling features in the IOMMU. Extending the same support as
> PASID feature discovery (pci_pasid_features) for PRI.
>
> Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS")
> Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Ashok Raj <ashok.raj@intel.com>
Cc: Lu Baolu <baolu.lu@intel.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
stable@vger.kernel.org, iommu@lists.linux-foundation.org,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v3 1/1] PCI/ATS: Check PRI supported on the PF device when SRIOV is enabled
Date: Fri, 24 Jul 2020 10:48:59 +0200 [thread overview]
Message-ID: <20200724084859.GQ27672@8bytes.org> (raw)
In-Reply-To: <1595543849-19692-1-git-send-email-ashok.raj@intel.com>
On Thu, Jul 23, 2020 at 03:37:29PM -0700, Ashok Raj wrote:
> PASID and PRI capabilities are only enumerated in PF devices. VF devices
> do not enumerate these capabilites. IOMMU drivers also need to enumerate
> them before enabling features in the IOMMU. Extending the same support as
> PASID feature discovery (pci_pasid_features) for PRI.
>
> Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS")
> Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
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next prev parent reply other threads:[~2020-07-24 8:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-23 22:37 [PATCH v3 1/1] PCI/ATS: Check PRI supported on the PF device when SRIOV is enabled Ashok Raj
2020-07-23 22:37 ` Ashok Raj
2020-07-23 23:54 ` Bjorn Helgaas
2020-07-23 23:54 ` Bjorn Helgaas
2020-07-24 2:32 ` Lu Baolu
2020-07-24 2:32 ` Lu Baolu
2020-07-24 8:48 ` Joerg Roedel [this message]
2020-07-24 8:48 ` Joerg Roedel
2020-07-24 14:51 ` Bjorn Helgaas
2020-07-24 14:51 ` Bjorn Helgaas
2020-07-27 21:24 ` Sasha Levin
2020-07-27 21:24 ` Sasha Levin
2020-07-28 16:31 ` Raj, Ashok
2020-07-28 16:31 ` Raj, Ashok
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