From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v5 25/36] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Fri, 14 Aug 2020 03:06:10 +0300 [thread overview] Message-ID: <20200814000621.8415-26-digetx@gmail.com> (raw) In-Reply-To: <20200814000621.8415-1-digetx@gmail.com> Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..629ad101c43b 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +137,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +648,17 @@ mc: memory-controller@7000f000 { interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v5 25/36] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Fri, 14 Aug 2020 03:06:10 +0300 [thread overview] Message-ID: <20200814000621.8415-26-digetx@gmail.com> (raw) In-Reply-To: <20200814000621.8415-1-digetx@gmail.com> Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..629ad101c43b 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +137,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +648,17 @@ mc: memory-controller@7000f000 { interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-08-14 0:08 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-14 0:05 [PATCH v5 00/36] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 01/36] clk: Export clk_hw_reparent() Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 02/36] clk: tegra: Remove Memory Controller lock Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 03/36] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 04/36] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 05/36] memory: tegra30-emc: " Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 06/36] memory: tegra124-emc: " Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 07/36] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 08/36] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 09/36] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 10/36] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 11/36] PM / devfreq: tegra30: " Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 12/36] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 1:00 ` Chanwoo Choi 2020-08-14 1:00 ` Chanwoo Choi 2020-08-14 0:05 ` [PATCH v5 13/36] PM / devfreq: tegra30: " Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 2:02 ` Chanwoo Choi 2020-08-14 2:02 ` Chanwoo Choi 2020-08-14 16:47 ` Dmitry Osipenko 2020-08-14 16:47 ` Dmitry Osipenko 2020-08-28 1:47 ` Chanwoo Choi 2020-08-28 1:47 ` Chanwoo Choi 2020-08-28 8:30 ` Dmitry Osipenko 2020-08-28 8:30 ` Dmitry Osipenko 2020-08-14 0:05 ` [PATCH v5 14/36] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko 2020-08-14 0:05 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 15/36] PM / devfreq: tegra30: " Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 16/36] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 17/36] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 18/36] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 19/36] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 20/36] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 21/36] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 22/36] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-25 2:09 ` Rob Herring 2020-08-25 2:09 ` Rob Herring 2020-08-14 0:06 ` [PATCH v5 23/36] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 24/36] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko [this message] 2020-08-14 0:06 ` [PATCH v5 25/36] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 26/36] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 27/36] memory: tegra-mc: Register as interconnect provider Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-09-09 8:31 ` Georgi Djakov 2020-09-09 8:31 ` Georgi Djakov 2020-09-09 21:15 ` Dmitry Osipenko 2020-09-09 21:15 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 28/36] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 29/36] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-09-09 8:32 ` Georgi Djakov 2020-09-09 8:32 ` Georgi Djakov 2020-08-14 0:06 ` [PATCH v5 31/36] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 32/36] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 33/36] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-09-09 8:32 ` Georgi Djakov 2020-09-09 8:32 ` Georgi Djakov 2020-08-14 0:06 ` [PATCH v5 34/36] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 35/36] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko 2020-08-14 0:06 ` [PATCH v5 36/36] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-08-14 0:06 ` Dmitry Osipenko
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