From: Karthik B S <karthik.b.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, michel@daenzer.net,
Karthik B S <karthik.b.s@intel.com>,
dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com,
uma.shankar@intel.com, daniel.vetter@intel.com,
nicholas.kazlauskas@amd.com
Subject: [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit
Date: Mon, 14 Sep 2020 11:26:31 +0530 [thread overview]
Message-ID: <20200914055633.21109-7-karthik.b.s@intel.com> (raw)
In-Reply-To: <20200914055633.21109-1-karthik.b.s@intel.com>
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0c17d94daf3..b7e24dff0772 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_enable_pipe_crc(crtc);
}
+static void skl_toggle_async_sync(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_plane *plane;
+ struct intel_plane_state *new_plane_state;
+ u32 update_mask = new_crtc_state->update_planes;
+ u32 plane_ctl, surf_addr;
+ enum plane_id plane_id;
+ unsigned long irqflags;
+ enum pipe pipe;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+ if (crtc->pipe != plane->pipe ||
+ !(update_mask & BIT(plane->id)))
+ continue;
+
+ plane_id = plane->id;
+ pipe = plane->pipe;
+
+ plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
+ surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
+
+ plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ }
+
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
+}
+
static void intel_update_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
else
intel_fbc_enable(state, crtc);
+ /* WA for older platforms where async address update enable bit
+ * is double buffered.
+ */
+ if (old_crtc_state->uapi.async_flip &&
+ !new_crtc_state->uapi.async_flip &&
+ INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
+ skl_toggle_async_sync(state, crtc, new_crtc_state);
+
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(new_crtc_state);
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Karthik B S <karthik.b.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, michel@daenzer.net,
dri-devel@lists.freedesktop.org, daniel.vetter@intel.com,
harry.wentland@amd.com, nicholas.kazlauskas@amd.com
Subject: [Intel-gfx] [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit
Date: Mon, 14 Sep 2020 11:26:31 +0530 [thread overview]
Message-ID: <20200914055633.21109-7-karthik.b.s@intel.com> (raw)
In-Reply-To: <20200914055633.21109-1-karthik.b.s@intel.com>
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0c17d94daf3..b7e24dff0772 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_enable_pipe_crc(crtc);
}
+static void skl_toggle_async_sync(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_plane *plane;
+ struct intel_plane_state *new_plane_state;
+ u32 update_mask = new_crtc_state->update_planes;
+ u32 plane_ctl, surf_addr;
+ enum plane_id plane_id;
+ unsigned long irqflags;
+ enum pipe pipe;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+ if (crtc->pipe != plane->pipe ||
+ !(update_mask & BIT(plane->id)))
+ continue;
+
+ plane_id = plane->id;
+ pipe = plane->pipe;
+
+ plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
+ surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
+
+ plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+ }
+
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
+}
+
static void intel_update_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
else
intel_fbc_enable(state, crtc);
+ /* WA for older platforms where async address update enable bit
+ * is double buffered.
+ */
+ if (old_crtc_state->uapi.async_flip &&
+ !new_crtc_state->uapi.async_flip &&
+ INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
+ skl_toggle_async_sync(state, crtc, new_crtc_state);
+
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(new_crtc_state);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-09-14 6:23 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-14 5:56 [PATCH v8 0/8] Asynchronous flip implementation for i915 Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-15 13:47 ` Ville Syrjälä
2020-09-15 13:47 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:36 ` Karthik B S
2020-09-16 12:36 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 2/8] drm/i915: Add support for async flips in I915 Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-15 13:48 ` Ville Syrjälä
2020-09-15 13:48 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:38 ` Karthik B S
2020-09-16 12:38 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 3/8] drm/i915: Add checks specific to async flips Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-15 14:03 ` Ville Syrjälä
2020-09-15 14:03 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:44 ` Karthik B S
2020-09-16 12:44 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-15 14:07 ` Ville Syrjälä
2020-09-15 14:07 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:46 ` Karthik B S
2020-09-16 12:46 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-15 14:10 ` Ville Syrjälä
2020-09-15 14:10 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:48 ` Karthik B S
2020-09-16 12:48 ` [Intel-gfx] " Karthik B S
2020-09-15 14:41 ` Ville Syrjälä
2020-09-15 14:41 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 13:00 ` Karthik B S
2020-09-16 13:00 ` [Intel-gfx] " Karthik B S
2020-09-16 15:52 ` Karthik B S
2020-09-16 15:52 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` Karthik B S [this message]
2020-09-14 5:56 ` [Intel-gfx] [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit Karthik B S
2020-09-15 14:19 ` Ville Syrjälä
2020-09-15 14:19 ` [Intel-gfx] " Ville Syrjälä
2020-09-16 12:54 ` Karthik B S
2020-09-16 12:54 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 7/8] Documentation/gpu: Add asynchronous flip documentation for i915 Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-14 5:56 ` [PATCH v8 8/8] drm/i915: Enable async flips in i915 Karthik B S
2020-09-14 5:56 ` [Intel-gfx] " Karthik B S
2020-09-14 11:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev8) Patchwork
2020-09-14 11:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-14 11:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-14 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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