From: Andre Przywara <andre.przywara@arm.com>
To: Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Leo Yan <leo.yan@linaro.org>, Tan Xiaojun <tanxiaojun@huawei.com>,
James Clark <james.clark@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register
Date: Tue, 22 Sep 2020 11:12:21 +0100 [thread overview]
Message-ID: <20200922101225.183554-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com>
The ARMv8.3-SPE extension adds some new bits for the event filter.
Remove bits 11, 17 and 18 from the RES0 mask, so they can be used
correctly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 554a7e8ecb07..efca4ee28671 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -281,7 +281,7 @@
#define SYS_PMSFCR_EL1_ST_SHIFT 18
#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
+#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL
#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
linux-kernel@vger.kernel.org, James Clark <james.clark@arm.com>,
Leo Yan <leo.yan@linaro.org>, Namhyung Kim <namhyung@kernel.org>,
Jiri Olsa <jolsa@redhat.com>, Tan Xiaojun <tanxiaojun@huawei.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register
Date: Tue, 22 Sep 2020 11:12:21 +0100 [thread overview]
Message-ID: <20200922101225.183554-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com>
The ARMv8.3-SPE extension adds some new bits for the event filter.
Remove bits 11, 17 and 18 from the RES0 mask, so they can be used
correctly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 554a7e8ecb07..efca4ee28671 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -281,7 +281,7 @@
#define SYS_PMSFCR_EL1_ST_SHIFT 18
#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
+#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL
#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
--
2.17.1
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next prev parent reply other threads:[~2020-09-22 10:12 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-22 10:12 [PATCH 0/5] perf: arm64: Support ARMv8.3-SPE extensions Andre Przywara
2020-09-22 10:12 ` Andre Przywara
2020-09-22 10:12 ` Andre Przywara [this message]
2020-09-22 10:12 ` [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register Andre Przywara
2020-09-27 2:51 ` Leo Yan
2020-09-27 2:51 ` Leo Yan
2020-09-22 10:12 ` [PATCH 2/5] perf: arm_spe: Add new event packet bits Andre Przywara
2020-09-22 10:12 ` Andre Przywara
2020-09-27 3:03 ` Leo Yan
2020-09-27 3:03 ` Leo Yan
2020-09-22 10:12 ` [PATCH 3/5] perf: arm_spe: Add nested virt event decoding Andre Przywara
2020-09-22 10:12 ` Andre Przywara
2020-09-27 3:11 ` Leo Yan
2020-09-27 3:11 ` Leo Yan
2020-09-22 10:12 ` [PATCH 4/5] perf: arm_spe: Decode memory tagging properties Andre Przywara
2020-09-22 10:12 ` Andre Przywara
2020-09-27 3:19 ` Leo Yan
2020-09-27 3:19 ` Leo Yan
2020-10-13 14:51 ` Arnaldo Carvalho de Melo
2020-10-13 14:52 ` Arnaldo Carvalho de Melo
2020-10-13 14:52 ` Arnaldo Carvalho de Melo
2020-09-22 10:12 ` [PATCH 5/5] perf: arm_spe: Decode SVE events Andre Przywara
2020-09-22 10:12 ` Andre Przywara
2020-09-27 3:30 ` Leo Yan
2020-09-27 3:30 ` Leo Yan
2020-09-28 10:15 ` André Przywara
2020-09-28 10:15 ` André Przywara
2020-09-28 11:08 ` Leo Yan
2020-09-28 11:08 ` Leo Yan
2020-09-28 13:21 ` Dave Martin
2020-09-28 13:21 ` Dave Martin
2020-09-28 13:59 ` André Przywara
2020-09-28 13:59 ` André Przywara
2020-09-28 14:47 ` Dave Martin
2020-09-28 14:47 ` Dave Martin
2020-09-29 2:19 ` Leo Yan
2020-09-29 2:19 ` Leo Yan
2020-09-29 14:03 ` Dave Martin
2020-09-29 14:03 ` Dave Martin
2020-09-30 10:34 ` Dave Martin
2020-09-30 10:34 ` Dave Martin
2020-09-30 11:04 ` Leo Yan
2020-09-30 11:04 ` Leo Yan
2020-10-05 10:15 ` Dave Martin
2020-10-05 10:15 ` Dave Martin
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