From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping
Date: Tue, 29 Sep 2020 23:42:22 -0700 [thread overview]
Message-ID: <20200930064234.85769-13-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200930064234.85769-1-lucas.demarchi@intel.com>
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
The values for VBT seem wrong in BSpec. For the current boards we
actually have a 1:1 mapping.
BSpec: 49311, 49945, 20124
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 ++++++++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4716484af62d..23bf21ee58ea 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1602,7 +1602,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e6b8d6dfb598..b0d71bbbf2ad 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return &gmbus_pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return &gmbus_pins_icp[pin];
else if (HAS_PCH_CNP(dev_priv))
return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
else if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3f2008d845c2..19ab23055c5e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3139,6 +3139,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3176,7 +3181,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.28.0
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next prev parent reply other threads:[~2020-09-30 6:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 6:42 [Intel-gfx] [PATCH v6 00/24] Introduce DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 01/24] drm/i915/dg1: add more PCI ids Lucas De Marchi
2020-09-30 14:00 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 02/24] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 03/24] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 04/24] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-09-30 15:44 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 05/24] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 06/24] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 07/24] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 08/24] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 09/24] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 10/24] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 11/24] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-09-30 6:42 ` Lucas De Marchi [this message]
2020-09-30 16:17 ` [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 13/24] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 14/24] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 15/24] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 16/24] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 17/24] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 18/24] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 19/24] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-09-30 17:33 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC Lucas De Marchi
2020-09-30 16:10 ` Matt Roper
2020-09-30 16:18 ` Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 21/24] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 22/24] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-09-30 16:50 ` Matt Roper
2020-10-08 4:20 ` Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-09-30 17:20 ` Matt Roper
2020-10-01 5:16 ` Lucas De Marchi
2020-10-01 14:51 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 24/24] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-09-30 7:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-09-30 7:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-30 7:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-09-30 8:01 ` Lucas De Marchi
2020-09-30 9:14 ` Matthew Auld
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