From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v6 13/24] drm/i915/dg1: Enable first 2 ports for DG1
Date: Tue, 29 Sep 2020 23:42:23 -0700 [thread overview]
Message-ID: <20200930064234.85769-14-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20200930064234.85769-1-lucas.demarchi@intel.com>
From: Aditya Swarup <aditya.swarup@intel.com>
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cb4e105c5ba6..3162ca6aaa0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7332,6 +7332,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_DG1(dev_priv))
+ /* FIXME: Enable only two ports for now */
+ return phy <= PHY_B;
else if (IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
@@ -7344,7 +7347,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -17101,7 +17104,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ /* FIXME: Enable only two ports for now */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
--
2.28.0
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next prev parent reply other threads:[~2020-09-30 6:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 6:42 [Intel-gfx] [PATCH v6 00/24] Introduce DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 01/24] drm/i915/dg1: add more PCI ids Lucas De Marchi
2020-09-30 14:00 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 02/24] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 03/24] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 04/24] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-09-30 15:44 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 05/24] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 06/24] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 07/24] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 08/24] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 09/24] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 10/24] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 11/24] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-09-30 16:17 ` Matt Roper
2020-09-30 6:42 ` Lucas De Marchi [this message]
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 14/24] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 15/24] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 16/24] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 17/24] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 18/24] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 19/24] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-09-30 17:33 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC Lucas De Marchi
2020-09-30 16:10 ` Matt Roper
2020-09-30 16:18 ` Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 21/24] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 22/24] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-09-30 16:50 ` Matt Roper
2020-10-08 4:20 ` Lucas De Marchi
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-09-30 17:20 ` Matt Roper
2020-10-01 5:16 ` Lucas De Marchi
2020-10-01 14:51 ` Matt Roper
2020-09-30 6:42 ` [Intel-gfx] [PATCH v6 24/24] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-09-30 7:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-09-30 7:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-30 7:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-09-30 8:01 ` Lucas De Marchi
2020-09-30 9:14 ` Matthew Auld
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