From: Jerome Brunet <jbrunet@baylibre.com>
To: Wolfram Sang <wsa@kernel.org>, Kevin Hilman <khilman@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Nicolas Belin <nbelin@baylibre.com>,
linux-i2c@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 0/3] i2c: meson: scl rate fixups
Date: Wed, 7 Oct 2020 10:07:48 +0200 [thread overview]
Message-ID: <20201007080751.1259442-1-jbrunet@baylibre.com> (raw)
This patchset fixes various issues related to SCL rate on AML SoCs.
We retain the method which was used so far to set the SCL rate.
This method does not provide manual control of the clock duty cycle
but so far it does seems to be a problem for anyone.
Amlogic vendor kernel source uses "HIGH/LOW" method which allows to set
the rate and the duty cycle of the clock. However the documentation
around this method could be better and the result on actual HW is not
perfectly aligned with the comments in AML code. In case the current
method ever becomes a problem, we might consider switching to this
HIGH/LOW method.
Jerome Brunet (2):
i2c: meson: fix clock setting overwrite
i2c: meson: keep peripheral clock enabled
Nicolas Belin (1):
i2c: meson: fixup rate calculation with filter delay
drivers/i2c/busses/i2c-meson.c | 52 +++++++++++++++++++++-------------
1 file changed, 33 insertions(+), 19 deletions(-)
--
2.25.4
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Wolfram Sang <wsa@kernel.org>, Kevin Hilman <khilman@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-i2c@vger.kernel.org, Nicolas Belin <nbelin@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>
Subject: [PATCH 0/3] i2c: meson: scl rate fixups
Date: Wed, 7 Oct 2020 10:07:48 +0200 [thread overview]
Message-ID: <20201007080751.1259442-1-jbrunet@baylibre.com> (raw)
This patchset fixes various issues related to SCL rate on AML SoCs.
We retain the method which was used so far to set the SCL rate.
This method does not provide manual control of the clock duty cycle
but so far it does seems to be a problem for anyone.
Amlogic vendor kernel source uses "HIGH/LOW" method which allows to set
the rate and the duty cycle of the clock. However the documentation
around this method could be better and the result on actual HW is not
perfectly aligned with the comments in AML code. In case the current
method ever becomes a problem, we might consider switching to this
HIGH/LOW method.
Jerome Brunet (2):
i2c: meson: fix clock setting overwrite
i2c: meson: keep peripheral clock enabled
Nicolas Belin (1):
i2c: meson: fixup rate calculation with filter delay
drivers/i2c/busses/i2c-meson.c | 52 +++++++++++++++++++++-------------
1 file changed, 33 insertions(+), 19 deletions(-)
--
2.25.4
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next reply other threads:[~2020-10-07 8:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 8:07 Jerome Brunet [this message]
2020-10-07 8:07 ` [PATCH 0/3] i2c: meson: scl rate fixups Jerome Brunet
2020-10-07 8:07 ` [PATCH 1/3] i2c: meson: fix clock setting overwrite Jerome Brunet
2020-10-07 8:07 ` Jerome Brunet
2020-10-08 9:59 ` Wolfram Sang
2020-10-08 9:59 ` Wolfram Sang
2020-10-07 8:07 ` [PATCH 2/3] i2c: meson: keep peripheral clock enabled Jerome Brunet
2020-10-07 8:07 ` Jerome Brunet
2020-10-08 10:00 ` Wolfram Sang
2020-10-08 10:00 ` Wolfram Sang
2020-10-07 8:07 ` [PATCH 3/3] i2c: meson: fixup rate calculation with filter delay Jerome Brunet
2020-10-07 8:07 ` Jerome Brunet
2020-10-08 10:00 ` Wolfram Sang
2020-10-08 10:00 ` Wolfram Sang
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