From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, daniel@ffwll.ch,
airlied@linux.ie, p.zabel@pengutronix.de,
chunkuang.hu@kernel.org, Fabien Parent <fparent@baylibre.com>
Subject: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Tue, 20 Oct 2020 19:42:47 +0200 [thread overview]
Message-ID: <20201020174253.3757771-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC. The SoC needs
an additional clock compared to the already supported SoC: mipi26m.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..10ae6be7225e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,12 +7,13 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
+- clock-names: must contain "engine", "digital", "hs"
+ Can optionnally also contain "mipi26m"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
@@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, daniel@ffwll.ch, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, p.zabel@pengutronix.de,
matthias.bgg@gmail.com
Subject: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Tue, 20 Oct 2020 19:42:47 +0200 [thread overview]
Message-ID: <20201020174253.3757771-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC. The SoC needs
an additional clock compared to the already supported SoC: mipi26m.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..10ae6be7225e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,12 +7,13 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
+- clock-names: must contain "engine", "digital", "hs"
+ Can optionnally also contain "mipi26m"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
@@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, daniel@ffwll.ch, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, p.zabel@pengutronix.de,
matthias.bgg@gmail.com
Subject: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Tue, 20 Oct 2020 19:42:47 +0200 [thread overview]
Message-ID: <20201020174253.3757771-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC. The SoC needs
an additional clock compared to the already supported SoC: mipi26m.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..10ae6be7225e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,12 +7,13 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
+- clock-names: must contain "engine", "digital", "hs"
+ Can optionnally also contain "mipi26m"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
@@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Cc: chunkuang.hu@kernel.org, airlied@linux.ie,
Fabien Parent <fparent@baylibre.com>,
robh+dt@kernel.org, matthias.bgg@gmail.com
Subject: [PATCH 2/8] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Date: Tue, 20 Oct 2020 19:42:47 +0200 [thread overview]
Message-ID: <20201020174253.3757771-3-fparent@baylibre.com> (raw)
In-Reply-To: <20201020174253.3757771-1-fparent@baylibre.com>
Add binding documentation for the MT8167 SoC. The SoC needs
an additional clock compared to the already supported SoC: mipi26m.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..10ae6be7225e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,12 +7,13 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
+- clock-names: must contain "engine", "digital", "hs"
+ Can optionnally also contain "mipi26m"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
@@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-20 17:43 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-20 17:42 [PATCH 0/8] Add DRM/DSI support for MT8167 SoC Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 1/8] dt-bindings: display: mediatek: disp: add documentation " Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-20 17:42 ` Fabien Parent [this message]
2020-10-20 17:42 ` [PATCH 2/8] dt-bindings: display: mediatek: dsi: " Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 3/8] drm/mediatek: add disp-color MT8167 support Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-20 17:42 ` [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-22 16:48 ` Fabien Parent
2020-10-22 16:48 ` Fabien Parent
2020-10-22 16:48 ` Fabien Parent
2020-10-22 16:48 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 5/8] drm/mediatek: dsi: add support for mipi26m clk Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 6/8] drm/mediatek: dsi: add support for MT8167 SoC Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 7/8] drm/mediatek: add DDP support for MT8167 Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-20 17:42 ` [PATCH 8/8] drm/mediatek: Add support for main DDP path on MT8167 Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
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