From: Fabien Parent <fparent@baylibre.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: "moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DTML <devicetree@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Daniel Vetter <daniel@ffwll.ch>,
David Airlie <airlied@linux.ie>,
Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
Date: Thu, 22 Oct 2020 18:48:54 +0200 [thread overview]
Message-ID: <CAOwMV_yybF9j6GZpHfz3WjAHSQhQo=Ot+2frSkN6dpODe3nwCQ@mail.gmail.com> (raw)
In-Reply-To: <CAAOTY_9Y98yHq7GcypUMryG4jMEdrDJeCeRXEKX3mb5g39y+sg@mail.gmail.com>
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> 於 2020年10月21日 週三 上午1:43寫道：
> >
> > On MT8167, DSI seems to work fine only if we start the clk in HS mode.
> > If we don't start the clk in HS but try to switch later to HS, the
> > display does not work.
> >
> > This commit adds a platform data variable to be used to start the
> > DSI clk in HS mode at power on.
>
> This patch looks like a hack patch. If you cowork with Mediatek,
> please find out the correct solution or give a reasonable explanation.
> If you could not get help from Mediatek, I would wait for comment on
> this patch.
It seems that this workaround is because of a specific display and not
because of a specific issue of the MT8167 DSI IP. I will drop this
patch in v2.
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 4a188a942c38..461643c05689 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > bool has_shadow_ctl;
> > bool has_size_ctl;
> > + bool use_hs_on_power_on;
> > };
> >
> > struct mtk_dsi {
> > @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> >
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > - mtk_dsi_clk_hs_mode(dsi, 0);
> > + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
> >
> > return 0;
> > err_disable_engine_clk:
> > --
> > 2.28.0
> >
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: DTML <devicetree@vger.kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
Date: Thu, 22 Oct 2020 18:48:54 +0200 [thread overview]
Message-ID: <CAOwMV_yybF9j6GZpHfz3WjAHSQhQo=Ot+2frSkN6dpODe3nwCQ@mail.gmail.com> (raw)
In-Reply-To: <CAAOTY_9Y98yHq7GcypUMryG4jMEdrDJeCeRXEKX3mb5g39y+sg@mail.gmail.com>
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> 於 2020年10月21日 週三 上午1:43寫道：
> >
> > On MT8167, DSI seems to work fine only if we start the clk in HS mode.
> > If we don't start the clk in HS but try to switch later to HS, the
> > display does not work.
> >
> > This commit adds a platform data variable to be used to start the
> > DSI clk in HS mode at power on.
>
> This patch looks like a hack patch. If you cowork with Mediatek,
> please find out the correct solution or give a reasonable explanation.
> If you could not get help from Mediatek, I would wait for comment on
> this patch.
It seems that this workaround is because of a specific display and not
because of a specific issue of the MT8167 DSI IP. I will drop this
patch in v2.
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 4a188a942c38..461643c05689 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > bool has_shadow_ctl;
> > bool has_size_ctl;
> > + bool use_hs_on_power_on;
> > };
> >
> > struct mtk_dsi {
> > @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> >
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > - mtk_dsi_clk_hs_mode(dsi, 0);
> > + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
> >
> > return 0;
> > err_disable_engine_clk:
> > --
> > 2.28.0
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: DTML <devicetree@vger.kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
Date: Thu, 22 Oct 2020 18:48:54 +0200 [thread overview]
Message-ID: <CAOwMV_yybF9j6GZpHfz3WjAHSQhQo=Ot+2frSkN6dpODe3nwCQ@mail.gmail.com> (raw)
In-Reply-To: <CAAOTY_9Y98yHq7GcypUMryG4jMEdrDJeCeRXEKX3mb5g39y+sg@mail.gmail.com>
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> 於 2020年10月21日 週三 上午1:43寫道：
> >
> > On MT8167, DSI seems to work fine only if we start the clk in HS mode.
> > If we don't start the clk in HS but try to switch later to HS, the
> > display does not work.
> >
> > This commit adds a platform data variable to be used to start the
> > DSI clk in HS mode at power on.
>
> This patch looks like a hack patch. If you cowork with Mediatek,
> please find out the correct solution or give a reasonable explanation.
> If you could not get help from Mediatek, I would wait for comment on
> this patch.
It seems that this workaround is because of a specific display and not
because of a specific issue of the MT8167 DSI IP. I will drop this
patch in v2.
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 4a188a942c38..461643c05689 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > bool has_shadow_ctl;
> > bool has_size_ctl;
> > + bool use_hs_on_power_on;
> > };
> >
> > struct mtk_dsi {
> > @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> >
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > - mtk_dsi_clk_hs_mode(dsi, 0);
> > + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
> >
> > return 0;
> > err_disable_engine_clk:
> > --
> > 2.28.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Fabien Parent <fparent@baylibre.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: DTML <devicetree@vger.kernel.org>,
David Airlie <airlied@linux.ie>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode
Date: Thu, 22 Oct 2020 18:48:54 +0200 [thread overview]
Message-ID: <CAOwMV_yybF9j6GZpHfz3WjAHSQhQo=Ot+2frSkN6dpODe3nwCQ@mail.gmail.com> (raw)
In-Reply-To: <CAAOTY_9Y98yHq7GcypUMryG4jMEdrDJeCeRXEKX3mb5g39y+sg@mail.gmail.com>
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Fabien:
>
> Fabien Parent <fparent@baylibre.com> 於 2020年10月21日 週三 上午1:43寫道：
> >
> > On MT8167, DSI seems to work fine only if we start the clk in HS mode.
> > If we don't start the clk in HS but try to switch later to HS, the
> > display does not work.
> >
> > This commit adds a platform data variable to be used to start the
> > DSI clk in HS mode at power on.
>
> This patch looks like a hack patch. If you cowork with Mediatek,
> please find out the correct solution or give a reasonable explanation.
> If you could not get help from Mediatek, I would wait for comment on
> this patch.
It seems that this workaround is because of a specific display and not
because of a specific issue of the MT8167 DSI IP. I will drop this
patch in v2.
> Regards,
> Chun-Kuang.
>
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 4a188a942c38..461643c05689 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -175,6 +175,7 @@ struct mtk_dsi_driver_data {
> > const u32 reg_cmdq_off;
> > bool has_shadow_ctl;
> > bool has_size_ctl;
> > + bool use_hs_on_power_on;
> > };
> >
> > struct mtk_dsi {
> > @@ -671,7 +672,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> >
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > - mtk_dsi_clk_hs_mode(dsi, 0);
> > + mtk_dsi_clk_hs_mode(dsi, !!dsi->driver_data->use_hs_on_power_on);
> >
> > return 0;
> > err_disable_engine_clk:
> > --
> > 2.28.0
> >
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-10-22 16:49 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-20 17:42 [PATCH 0/8] Add DRM/DSI support for MT8167 SoC Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 1/8] dt-bindings: display: mediatek: disp: add documentation " Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-21 23:40 ` Chun-Kuang Hu
2020-10-20 17:42 ` [PATCH 2/8] dt-bindings: display: mediatek: dsi: " Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 17:01 ` Chun-Kuang Hu
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-21 18:56 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 3/8] drm/mediatek: add disp-color MT8167 support Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-21 23:42 ` Chun-Kuang Hu
2020-10-20 17:42 ` [PATCH 4/8] drm/mediatek: dsi: add pdata variable to start clk in HS mode Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-21 17:07 ` Chun-Kuang Hu
2020-10-22 16:48 ` Fabien Parent [this message]
2020-10-22 16:48 ` Fabien Parent
2020-10-22 16:48 ` Fabien Parent
2020-10-22 16:48 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 5/8] drm/mediatek: dsi: add support for mipi26m clk Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 6/8] drm/mediatek: dsi: add support for MT8167 SoC Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` [PATCH 7/8] drm/mediatek: add DDP support for MT8167 Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-21 23:56 ` Chun-Kuang Hu
2020-10-20 17:42 ` [PATCH 8/8] drm/mediatek: Add support for main DDP path on MT8167 Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
2020-10-20 17:42 ` Fabien Parent
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