From: Will Deacon <will@kernel.org> To: Catalin Marinas <catalin.marinas@arm.com> Cc: Morten Rasmussen <morten.rasmussen@arm.com>, Marc Zyngier <maz@kernel.org>, linux-arch@vger.kernel.org, "Peter Zijlstra (Intel)" <peterz@infradead.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, James Morse <james.morse@arm.com>, Linus Torvalds <torvalds@linux-foundation.org>, Qais Yousef <qais.yousef@arm.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Date: Wed, 21 Oct 2020 15:45:43 +0100 [thread overview] Message-ID: <20201021144542.GB17912@willie-the-truck> (raw) In-Reply-To: <20201021140945.GD3976@gaia> On Wed, Oct 21, 2020 at 03:09:46PM +0100, Catalin Marinas wrote: > On Wed, Oct 21, 2020 at 03:33:29PM +0200, Morten Rasmussen wrote: > > On Wed, Oct 21, 2020 at 01:15:59PM +0100, Catalin Marinas wrote: > > > one, though not as easy as automatic task placement by the scheduler (my > > > first preference, followed by the id_* regs and the aarch32 mask, though > > > not a strong preference for any). > > > > Automatic task placement by the scheduler would mean giving up the > > requirement that the user-space affinity mask must always be honoured. > > Is that on the table? > > I think Peter rejected it but I still find it a nicer interface from a > dumb application perspective. It may interact badly with cpusets though > (at least on Android). > > > Killing aarch32 tasks with an empty intersection between the > > user-space mask and aarch32_mask is not really "automatic" and would > > require the aarch32 capability to be exposed anyway. > > I agree, especially if overriding the user mask is not desirable. But if > one doesn't play around with cpusets, 32-bit apps would run "fine" with > the scheduler transparently placing them on the correct CPU. > > Anyway, if the task placement is entirely off the table, the next thing > is asking applications to set their own mask and kill them if they do > the wrong thing. Here I see two possibilities for killing an app: > > 1. When it ends up scheduled on a non-AArch32-capable CPU That sounds fine to me. If we could do the exception return and take a SIGILL, that's what we'd do, but we can't so we have to catch it before. > 2. If the user cpumask (bar the offline CPUs) is not a subset of the > aarch32_mask > > Option 1 is simpler but 2 would be slightly more consistent. I disagree -- if we did this for something like fpsimd, then the consistent behaviour would be to SIGILL on the cores without the instructions. > There's also the question on whether the kernel should allow an ELF32 to > be loaded (and potentially killed subsequently) if the user mask is not > correct on execve(). I don't see the point in distinguishing between "you did execve() on a core without 32-bit" and "you did execve() on a core with 32-bit and then migrated to a core without 32-bit". Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org> To: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arch@vger.kernel.org, "Peter Zijlstra \(Intel\)" <peterz@infradead.org>, Marc Zyngier <maz@kernel.org>, Qais Yousef <qais.yousef@arm.com>, James Morse <james.morse@arm.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Linus Torvalds <torvalds@linux-foundation.org>, Morten Rasmussen <morten.rasmussen@arm.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Date: Wed, 21 Oct 2020 15:45:43 +0100 [thread overview] Message-ID: <20201021144542.GB17912@willie-the-truck> (raw) In-Reply-To: <20201021140945.GD3976@gaia> On Wed, Oct 21, 2020 at 03:09:46PM +0100, Catalin Marinas wrote: > On Wed, Oct 21, 2020 at 03:33:29PM +0200, Morten Rasmussen wrote: > > On Wed, Oct 21, 2020 at 01:15:59PM +0100, Catalin Marinas wrote: > > > one, though not as easy as automatic task placement by the scheduler (my > > > first preference, followed by the id_* regs and the aarch32 mask, though > > > not a strong preference for any). > > > > Automatic task placement by the scheduler would mean giving up the > > requirement that the user-space affinity mask must always be honoured. > > Is that on the table? > > I think Peter rejected it but I still find it a nicer interface from a > dumb application perspective. It may interact badly with cpusets though > (at least on Android). > > > Killing aarch32 tasks with an empty intersection between the > > user-space mask and aarch32_mask is not really "automatic" and would > > require the aarch32 capability to be exposed anyway. > > I agree, especially if overriding the user mask is not desirable. But if > one doesn't play around with cpusets, 32-bit apps would run "fine" with > the scheduler transparently placing them on the correct CPU. > > Anyway, if the task placement is entirely off the table, the next thing > is asking applications to set their own mask and kill them if they do > the wrong thing. Here I see two possibilities for killing an app: > > 1. When it ends up scheduled on a non-AArch32-capable CPU That sounds fine to me. If we could do the exception return and take a SIGILL, that's what we'd do, but we can't so we have to catch it before. > 2. If the user cpumask (bar the offline CPUs) is not a subset of the > aarch32_mask > > Option 1 is simpler but 2 would be slightly more consistent. I disagree -- if we did this for something like fpsimd, then the consistent behaviour would be to SIGILL on the cores without the instructions. > There's also the question on whether the kernel should allow an ELF32 to > be loaded (and potentially killed subsequently) if the user mask is not > correct on execve(). I don't see the point in distinguishing between "you did execve() on a core without 32-bit" and "you did execve() on a core with 32-bit and then migrated to a core without 32-bit". Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-10-21 14:45 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-21 10:46 [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 1/4] arm64: kvm: Handle " Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 12:02 ` Marc Zyngier 2020-10-21 12:02 ` Marc Zyngier 2020-10-21 13:35 ` Qais Yousef 2020-10-21 13:35 ` Qais Yousef 2020-10-21 13:51 ` Marc Zyngier 2020-10-21 13:51 ` Marc Zyngier 2020-10-21 14:38 ` Qais Yousef 2020-10-21 14:38 ` Qais Yousef 2020-11-02 17:58 ` Qais Yousef 2020-11-02 17:58 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 2/4] arm64: Add support for asymmetric AArch32 EL0 configurations Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 15:39 ` Will Deacon 2020-10-21 15:39 ` Will Deacon 2020-10-21 16:21 ` Qais Yousef 2020-10-21 16:21 ` Qais Yousef 2020-10-21 16:52 ` Catalin Marinas 2020-10-21 16:52 ` Catalin Marinas 2020-10-21 17:39 ` Will Deacon 2020-10-21 17:39 ` Will Deacon 2020-10-22 9:53 ` Catalin Marinas 2020-10-22 9:53 ` Catalin Marinas 2020-10-21 10:46 ` [RFC PATCH v2 3/4] arm64: export emulate_sys_reg() Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 10:46 ` [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Qais Yousef 2020-10-21 10:46 ` Qais Yousef 2020-10-21 11:09 ` Marc Zyngier 2020-10-21 11:09 ` Marc Zyngier 2020-10-21 11:25 ` Greg Kroah-Hartman 2020-10-21 11:25 ` Greg Kroah-Hartman 2020-10-21 11:46 ` Marc Zyngier 2020-10-21 11:46 ` Marc Zyngier 2020-10-21 12:11 ` Greg Kroah-Hartman 2020-10-21 12:11 ` Greg Kroah-Hartman 2020-10-21 13:18 ` Qais Yousef 2020-10-21 13:18 ` Qais Yousef 2020-10-21 12:15 ` Catalin Marinas 2020-10-21 12:15 ` Catalin Marinas 2020-10-21 13:20 ` Qais Yousef 2020-10-21 13:20 ` Qais Yousef 2020-10-21 13:33 ` Morten Rasmussen 2020-10-21 13:33 ` Morten Rasmussen 2020-10-21 14:09 ` Catalin Marinas 2020-10-21 14:09 ` Catalin Marinas 2020-10-21 14:41 ` Morten Rasmussen 2020-10-21 14:41 ` Morten Rasmussen 2020-10-21 14:45 ` Will Deacon [this message] 2020-10-21 14:45 ` Will Deacon 2020-10-21 15:10 ` Catalin Marinas 2020-10-21 15:10 ` Catalin Marinas 2020-10-21 15:37 ` Will Deacon 2020-10-21 15:37 ` Will Deacon 2020-10-21 16:18 ` Catalin Marinas 2020-10-21 16:18 ` Catalin Marinas 2020-10-21 17:19 ` Will Deacon 2020-10-21 17:19 ` Will Deacon 2020-10-22 9:55 ` Morten Rasmussen 2020-10-22 9:55 ` Morten Rasmussen 2020-10-21 14:31 ` Qais Yousef 2020-10-21 14:31 ` Qais Yousef 2020-10-22 10:16 ` Morten Rasmussen 2020-10-22 10:16 ` Morten Rasmussen 2020-10-22 10:48 ` Qais Yousef 2020-10-22 10:48 ` Qais Yousef 2020-10-21 14:41 ` Will Deacon 2020-10-21 14:41 ` Will Deacon 2020-10-21 15:03 ` Qais Yousef 2020-10-21 15:03 ` Qais Yousef 2020-10-21 15:23 ` Will Deacon 2020-10-21 15:23 ` Will Deacon 2020-10-21 16:07 ` Qais Yousef 2020-10-21 16:07 ` Qais Yousef 2020-10-21 17:23 ` Will Deacon 2020-10-21 17:23 ` Will Deacon 2020-10-21 19:57 ` Qais Yousef 2020-10-21 19:57 ` Qais Yousef 2020-10-21 20:26 ` Will Deacon 2020-10-21 20:26 ` Will Deacon 2020-10-22 8:16 ` Catalin Marinas 2020-10-22 8:16 ` Catalin Marinas 2020-10-22 9:58 ` Qais Yousef 2020-10-22 9:58 ` Qais Yousef 2020-10-22 13:47 ` Qais Yousef 2020-10-22 13:47 ` Qais Yousef 2020-10-22 13:55 ` Greg Kroah-Hartman 2020-10-22 13:55 ` Greg Kroah-Hartman 2020-10-22 14:31 ` Catalin Marinas 2020-10-22 14:31 ` Catalin Marinas 2020-10-22 14:34 ` Qais Yousef 2020-10-22 14:34 ` Qais Yousef 2020-10-26 19:02 ` Qais Yousef 2020-10-26 19:02 ` Qais Yousef 2020-10-26 19:08 ` Greg Kroah-Hartman 2020-10-26 19:08 ` Greg Kroah-Hartman 2020-10-26 19:18 ` Qais Yousef 2020-10-26 19:18 ` Qais Yousef 2020-10-21 11:28 ` Greg Kroah-Hartman 2020-10-21 11:28 ` Greg Kroah-Hartman 2020-10-21 13:22 ` Qais Yousef 2020-10-21 13:22 ` Qais Yousef 2020-10-21 11:26 ` [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Greg Kroah-Hartman 2020-10-21 11:26 ` Greg Kroah-Hartman 2020-10-21 13:15 ` Qais Yousef 2020-10-21 13:15 ` Qais Yousef 2020-10-21 13:31 ` Greg Kroah-Hartman 2020-10-21 13:31 ` Greg Kroah-Hartman 2020-10-21 13:55 ` Qais Yousef 2020-10-21 13:55 ` Qais Yousef 2020-10-21 14:35 ` Catalin Marinas 2020-10-21 14:35 ` Catalin Marinas
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