From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes
Date: Tue, 27 Oct 2020 15:29:58 +0800 [thread overview]
Message-ID: <20201027073001.41808-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
3 files changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 6a2c09199047..0f63aea30477 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -512,6 +512,7 @@
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 0464b8aa4bc4..d33a64ae8b0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -837,6 +837,7 @@
<0000 0 0 2 &gic 0 111 0x4>,
<0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>;
+ big-endian;
status = "disabled";
};
@@ -863,6 +864,7 @@
<0000 0 0 2 &gic 0 121 0x4>,
<0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>;
+ big-endian;
status = "disabled";
};
@@ -889,6 +891,7 @@
<0000 0 0 2 &gic 0 155 0x4>,
<0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>;
+ big-endian;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 1fa39bacff4b..b01fb93f7d19 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -741,6 +741,7 @@
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -777,6 +778,7 @@
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -813,6 +815,7 @@
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
mingkai.hu@nxp.com, roy.zang@nxp.com
Subject: [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes
Date: Tue, 27 Oct 2020 15:29:58 +0800 [thread overview]
Message-ID: <20201027073001.41808-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
3 files changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 6a2c09199047..0f63aea30477 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -512,6 +512,7 @@
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 0464b8aa4bc4..d33a64ae8b0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -837,6 +837,7 @@
<0000 0 0 2 &gic 0 111 0x4>,
<0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>;
+ big-endian;
status = "disabled";
};
@@ -863,6 +864,7 @@
<0000 0 0 2 &gic 0 121 0x4>,
<0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>;
+ big-endian;
status = "disabled";
};
@@ -889,6 +891,7 @@
<0000 0 0 2 &gic 0 155 0x4>,
<0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>;
+ big-endian;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 1fa39bacff4b..b01fb93f7d19 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -741,6 +741,7 @@
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -777,6 +778,7 @@
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -813,6 +815,7 @@
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
--
2.17.1
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linux-arm-kernel@lists.infradead.org
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next prev parent reply other threads:[~2020-10-27 7:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 7:29 [PATCHv2 0/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 2/7] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou [this message]
2020-10-27 7:29 ` [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2020-10-27 7:29 ` [PATCHv2 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou
2020-10-27 7:29 ` Zhiqiang Hou
2020-10-27 7:30 ` [PATCHv2 6/7] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou
2020-10-27 7:30 ` Zhiqiang Hou
2020-10-27 7:30 ` [PATCHv2 7/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-10-27 7:30 ` Zhiqiang Hou
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