From: "Ramuthevar,Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: broonie@kernel.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org
Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com,
cheol.yong.kim@intel.com, qi-ming.wu@intel.com,
Ramuthevar Vadivel Murugan
<vadivel.muruganx.ramuthevar@linux.intel.com>
Subject: [PATCH v9 5/5] dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
Date: Tue, 24 Nov 2020 12:18:40 +0800 [thread overview]
Message-ID: <20201124041840.31066-6-vadivel.muruganx.ramuthevar@linux.intel.com> (raw)
In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com>
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add new vendor specific compatible string to check Intel's Lightning
Mountain(LGM) QSPI features enablement in cadence-quadspi driver.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/spi/cadence-quadspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
index 945be7d5b236..8ace832a2d80 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
@@ -5,6 +5,7 @@ Required properties:
Generic default - "cdns,qspi-nor".
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
+ For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: broonie@kernel.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org
Cc: cheol.yong.kim@intel.com, vigneshr@ti.com,
Ramuthevar Vadivel Murugan
<vadivel.muruganx.ramuthevar@linux.intel.com>,
linux-mtd@lists.infradead.org, qi-ming.wu@intel.com,
p.yadav@ti.com
Subject: [PATCH v9 5/5] dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
Date: Tue, 24 Nov 2020 12:18:40 +0800 [thread overview]
Message-ID: <20201124041840.31066-6-vadivel.muruganx.ramuthevar@linux.intel.com> (raw)
In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com>
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add new vendor specific compatible string to check Intel's Lightning
Mountain(LGM) QSPI features enablement in cadence-quadspi driver.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/spi/cadence-quadspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
index 945be7d5b236..8ace832a2d80 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
@@ -5,6 +5,7 @@ Required properties:
Generic default - "cdns,qspi-nor".
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
+ For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.11.0
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next prev parent reply other threads:[~2020-11-24 4:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 4:18 [PATCH v9 0/5] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar, Vadivel MuruganX
2020-11-24 4:18 ` [PATCH v9 1/5] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar, Vadivel MuruganX
2020-11-24 4:18 ` [PATCH v9 2/5] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar, Vadivel MuruganX
2020-11-24 4:18 ` [PATCH v9 3/5] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar, Vadivel MuruganX
2020-11-24 4:18 ` [PATCH v9 4/5] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar, Vadivel MuruganX
2020-11-24 4:18 ` Ramuthevar,Vadivel MuruganX [this message]
2020-11-24 4:18 ` [PATCH v9 5/5] dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi Ramuthevar, Vadivel MuruganX
2021-01-13 15:28 ` [PATCH v9 0/5] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Mark Brown
2021-01-13 15:28 ` Mark Brown
2021-01-14 3:35 ` Kim, Cheol Yong
2021-01-14 3:35 ` Kim, Cheol Yong
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