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From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Anshuman Gupta <anshuman.gupta@intel.com>,
	Uma Shankar <uma.shankar@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [RFC PATCH 120/162] drm/i915/oprom: Basic sanitization
Date: Fri, 27 Nov 2020 12:06:36 +0000	[thread overview]
Message-ID: <20201127120718.454037-121-matthew.auld@intel.com> (raw)
In-Reply-To: <20201127120718.454037-1-matthew.auld@intel.com>

From: Anshuman Gupta <anshuman.gupta@intel.com>

Sanitize OPROM header, CPD signature and OPROM PCI version.
OPROM_HEADER, EXPANSION_ROM_HEADER and OPROM_MEU_BLOB structures
and PCI struct offsets are provided by GSC counterparts.
These are yet to be Documented in B.Spec.
After successful sanitization, extract VBT from opregion
image.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     |  49 +++--
 drivers/gpu/drm/i915/display/intel_opregion.c | 169 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  31 +++-
 3 files changed, 221 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 91044fc52acb..358576bc0be2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2088,37 +2088,36 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
 
 static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *dev_priv)
 {
-	u32 count, data, found, store = 0;
-	u32 static_region, oprom_offset;
-	u32 oprom_size = 0x200000;
-	u16 vbt_size;
-	u32 *vbt;
-
-	static_region = I915_READ(SPI_STATIC_REGIONS);
-	static_region &= OPTIONROM_SPI_REGIONID_MASK;
-	I915_WRITE(PRIMARY_SPI_REGIONID, static_region);
+	u32 count, found;
+	u32 *vbt, *oprom_opreg = NULL;
+	u16 vbt_size, opreg_size;
+	u8 *parse_ptr;
 
-	oprom_offset = I915_READ(OROM_OFFSET);
-	oprom_offset &= OROM_OFFSET_MASK;
+	if (intel_oprom_verify_signature(&oprom_opreg, &opreg_size, dev_priv)) {
+		drm_err(&dev_priv->drm, "oprom signature verification failed\n");
+		goto err_not_found;
+	}
 
-	for (count = 0; count < oprom_size; count += 4) {
-		I915_WRITE(PRIMARY_SPI_ADDRESS, oprom_offset + count);
-		data = I915_READ(PRIMARY_SPI_TRIGGER);
+	if (!oprom_opreg) {
+		drm_err(&dev_priv->drm, "opregion not found\n");
+		goto err_not_found;
+	}
 
-		if (data == *((const u32 *)"$VBT")) {
-			found = oprom_offset + count;
+	for (count = 0; count < opreg_size; count += 4) {
+		if (oprom_opreg[count / 4] == *((const u32 *)"$VBT")) {
+			found = count;
 			break;
 		}
 	}
 
-	if (count >= oprom_size)
+	if (count >= opreg_size) {
+		drm_err(&dev_priv->drm, "VBT not found in opregion\n");
 		goto err_not_found;
+	}
 
 	/* Get VBT size and allocate space for the VBT */
-	I915_WRITE(PRIMARY_SPI_ADDRESS, found +
-		   offsetof(struct vbt_header, vbt_size));
-	vbt_size = I915_READ(PRIMARY_SPI_TRIGGER);
-	vbt_size &= 0xffff;
+	parse_ptr = (u8 *)oprom_opreg + found;
+	vbt_size = ((struct vbt_header *)parse_ptr)->vbt_size;
 
 	vbt = kzalloc(vbt_size, GFP_KERNEL);
 	if (!vbt) {
@@ -2127,16 +2126,12 @@ static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *dev_priv)
 		goto err_not_found;
 	}
 
-	for (count = 0; count < vbt_size; count += 4) {
-		I915_WRITE(PRIMARY_SPI_ADDRESS, found + count);
-		data = I915_READ(PRIMARY_SPI_TRIGGER);
-		*(vbt + store++) = data;
-	}
-
+	memcpy(vbt, parse_ptr, vbt_size);
 	if (!intel_bios_is_valid_vbt(vbt, vbt_size))
 		goto err_free_vbt;
 
 	DRM_DEBUG_KMS("Found valid VBT in SPI flash\n");
+	kfree(oprom_opreg);
 
 	return (struct vbt_header *)vbt;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 4f77cf849171..81e5946393dd 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -983,6 +983,175 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 	return err;
 }
 
+static int oprom_image_parse_helper(u8 *parse_ptr, u8 *last_img, u8 *code_type,
+				    struct drm_i915_private *i915)
+{
+	u8 size_512_bytes;
+
+	if (((union oprom_header *)parse_ptr)->signature != OPROM_IMAGE_MAGIC) {
+		drm_err(&i915->drm, "Wrong OPROM header signature.\n");
+		return -EINVAL;
+	}
+
+	size_512_bytes = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_IMAGE_LENGTH_OFFSET];
+	*code_type = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_CODE_TYPE_OFFSET];
+	*last_img = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_LAST_IMAGE_INDICATOR_OFFSET];
+
+	return size_512_bytes;
+}
+
+static void spi_read_oprom_helper(size_t len, u32 offset, u32 *buf,
+				  struct drm_i915_private *dev_priv)
+{
+	u32 count, data;
+
+	for (count = 0; count < len; count += 4) {
+		I915_WRITE(PRIMARY_SPI_ADDRESS, offset + count);
+		data = I915_READ(PRIMARY_SPI_TRIGGER);
+		buf[count / 4] = data;
+	}
+}
+
+/**
+ *	+        DASH+G OPROM IMAGE LAYOUT           +
+ *	+--------+-------+---------------------------+
+ *	| Offset | Value |   ROM Header Fields       +-----> Image 1 (CSS)
+ *	+--------------------------------------------+
+ *	|    0h  |  55h  |   ROM Signature Byte1     |
+ *	|    1h  |  AAh  |   ROM Signature Byte2     |
+ *	|    2h  |  xx   |        Reserved           |
+ *	|  18+19h|  xx   |  Ptr to PCI DataStructure |
+ *	+----------------+---------------------------+
+ *	|           PCI Data Structure               |
+ *	+--------------------------------------------+
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|    10  +  xx   +     Image Length          |
+ *	|    14  +  xx   +     Code Type             |
+ *	|    15  +  xx   +  Last Image Indicator     |
+ *	|    .       .             .                 |
+ *	+--------------------------------------------+
+ *	|               MEU BLOB                     |
+ *	+--------------------------------------------+
+ *	|              CPD Header                    |
+ *	|              CPD Entry                     |
+ *	|              Reserved                      |
+ *	|           SignedDataPart1                  |
+ *	|              PublicKey                     |
+ *	|            RSA Signature                   |
+ *	|           SignedDataPart2                  |
+ *	|            IFWI Metadata                   |
+ *	+--------+-------+---------------------------+
+ *	|    .   |   .   |         .                 |
+ *	|    .   |   .   |         .                 |
+ *	+--------------------------------------------+
+ *	| Offset | Value |   ROM Header Fields       +-----> Image 2 (Config Data) (Offset: 0x800)
+ *	+--------------------------------------------+
+ *	|    0h  |  55h  |   ROM Signature Byte1     |
+ *	|    1h  |  AAh  |   ROM Signature Byte2     |
+ *	|    2h  |  xx   |        Reserved           |
+ *	|  18+19h|  xx   |  Ptr to PCI DataStructure |
+ *	+----------------+---------------------------+
+ *	|           PCI Data Structure               |
+ *	+--------------------------------------------+
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|    10  +  xx   +     Image Length          |
+ *	|    14  +  xx   +      Code Type            |
+ *	|    15  +  xx   +   Last Image Indicator    |
+ *	|    .       .             .                 |
+ *	|    1A  +  3C   + Ptr to Opregion Signature |
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|   83Ch + IntelGraphicsMem                  | <---+ Opregion Signature
+ *	+--------+-----------------------------------+
+ *
+ * intel_oprom_verify_signature() verify OPROM signature.
+ * @opreg: pointer to opregion buffer output.
+ * @opreg_size: pointer to opregion size output.
+ * @dev_priv: i915 device.
+ */
+int
+intel_oprom_verify_signature(u32 **opreg, u16 *opreg_size,
+			     struct drm_i915_private *dev_priv)
+{
+	u8 img_sig[sizeof(OPREGION_SIGNATURE)];
+	u8 code_type, last_img;
+	u32 static_region, offset;
+	u32 *oprom_img, *oprom_img_hdr;
+	u16 opreg_base, img_len;
+	u8 *parse_ptr;
+	int img_size;
+	int ret = -EINVAL;
+
+	/* initialize SPI to read the OPROM */
+	static_region = I915_READ(SPI_STATIC_REGIONS);
+	static_region &= OPTIONROM_SPI_REGIONID_MASK;
+	I915_WRITE(PRIMARY_SPI_REGIONID, static_region);
+	/* read OPROM offset in SPI flash */
+	offset = I915_READ(OROM_OFFSET);
+	offset &= OROM_OFFSET_MASK;
+
+	oprom_img_hdr = kzalloc(OPROM_INITIAL_READ_SIZE, GFP_KERNEL);
+	if (!oprom_img_hdr)
+		return -ENOMEM;
+
+	do {
+		spi_read_oprom_helper(OPROM_INITIAL_READ_SIZE, offset,
+				      oprom_img_hdr, dev_priv);
+		img_size = oprom_image_parse_helper((u8 *)oprom_img_hdr, &last_img,
+						    &code_type, dev_priv);
+		if (img_size <= 0) {
+			ret = -EINVAL;
+			goto err_free_hdr;
+		}
+
+		img_len = img_size * OPROM_BYTE_BOUNDARY;
+		oprom_img = kzalloc(img_len, GFP_KERNEL);
+		if (!oprom_img) {
+			ret = -ENOMEM;
+			goto err_free_hdr;
+		}
+
+		spi_read_oprom_helper(img_len, offset, oprom_img, dev_priv);
+		parse_ptr = (u8 *)oprom_img;
+		offset = offset + img_len;
+
+		/* opregion base offset */
+		opreg_base = ((struct expansion_rom_header *)parse_ptr)->opregion_base;
+		/* CPD or opreg signature is present at opregion_base offset */
+		memcpy(img_sig, parse_ptr + opreg_base, sizeof(OPREGION_SIGNATURE));
+
+		if (!memcmp(img_sig, OPREGION_SIGNATURE, sizeof(OPREGION_SIGNATURE) - 1)) {
+			*opreg = oprom_img;
+			*opreg_size = img_len;
+			drm_dbg_kms(&dev_priv->drm, "Found opregion image\n");
+			ret = 0;
+			break;
+		} else if (!memcmp(img_sig, CPD_SIGNATURE, NUM_CPD_BYTES)) {
+			if (code_type != OPROM_CSS_CODE_TYPE) {
+				drm_err(&dev_priv->drm, "Invalid OPROM\n");
+				ret = -EINVAL;
+				goto err_free_img;
+			}
+			drm_dbg_kms(&dev_priv->drm, "Found CSS image\n");
+			/* proceed here onwards for signature authentication */
+			kfree(oprom_img);
+			continue;
+		}
+
+	} while (last_img != LAST_IMG_INDICATOR);
+
+	return ret;
+
+err_free_img:
+	kfree(oprom_img);
+err_free_hdr:
+	kfree(oprom_img_hdr);
+
+	return ret;
+}
+
 static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id)
 {
 	DRM_INFO("Using panel type from OpRegion on %s\n", id->ident);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 4aa68ffbd30e..4e2eeadf101e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -54,6 +54,34 @@ struct intel_opregion {
 
 #define OPREGION_SIZE            (8 * 1024)
 
+#define CPD_SIGNATURE "$CPD"                  /* CPD Signature */
+#define NUM_CPD_BYTES 4
+#define PCI_IMAGE_LENGTH_OFFSET 0x10
+#define PCI_CODE_TYPE_OFFSET 0x14
+#define PCI_LAST_IMAGE_INDICATOR_OFFSET 0x15
+#define LAST_IMG_INDICATOR 0x80
+#define OPROM_IMAGE_MAGIC 0xAA55       /* Little Endian */
+#define OPROM_CSS_CODE_TYPE 0xF0
+#define OPROM_BYTE_BOUNDARY 512        /* OPROM image sizes are indicated in 512 byte boundaries */
+#define OPROM_INITIAL_READ_SIZE 60     /* Read 60 bytes to compute the Img Len from PCI structure */
+
+union oprom_header {
+	u32 data;
+	struct {
+		u16 signature;  /* Offset[0x0]: Header 0x55 0xAA */
+		u8 sizein512bytes;
+		u8 reserved;
+	};
+};
+
+struct expansion_rom_header {
+	union oprom_header header;      /* Offset[0x0]: Oprom Header */
+	u16 vbiospostoffset;    /* Offset[0x4]: pointer to VBIOS entry point */
+	u8 resvd[0x12];
+	u16 pcistructoffset;    /* Offset[0x18]: Contains pointer PCI Data Structure */
+	u16 opregion_base;      /* Offset[0x1A]: Offset to Opregion Base start */
+};
+
 #ifdef CONFIG_ACPI
 
 int intel_opregion_setup(struct drm_i915_private *dev_priv);
@@ -118,5 +146,6 @@ static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
 }
 
 #endif /* CONFIG_ACPI */
-
+int intel_oprom_verify_signature(u32 **opreg, u16 *opreg_size,
+				 struct drm_i915_private *i915);
 #endif
-- 
2.26.2

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WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [RFC PATCH 120/162] drm/i915/oprom: Basic sanitization
Date: Fri, 27 Nov 2020 12:06:36 +0000	[thread overview]
Message-ID: <20201127120718.454037-121-matthew.auld@intel.com> (raw)
In-Reply-To: <20201127120718.454037-1-matthew.auld@intel.com>

From: Anshuman Gupta <anshuman.gupta@intel.com>

Sanitize OPROM header, CPD signature and OPROM PCI version.
OPROM_HEADER, EXPANSION_ROM_HEADER and OPROM_MEU_BLOB structures
and PCI struct offsets are provided by GSC counterparts.
These are yet to be Documented in B.Spec.
After successful sanitization, extract VBT from opregion
image.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     |  49 +++--
 drivers/gpu/drm/i915/display/intel_opregion.c | 169 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  31 +++-
 3 files changed, 221 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 91044fc52acb..358576bc0be2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2088,37 +2088,36 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
 
 static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *dev_priv)
 {
-	u32 count, data, found, store = 0;
-	u32 static_region, oprom_offset;
-	u32 oprom_size = 0x200000;
-	u16 vbt_size;
-	u32 *vbt;
-
-	static_region = I915_READ(SPI_STATIC_REGIONS);
-	static_region &= OPTIONROM_SPI_REGIONID_MASK;
-	I915_WRITE(PRIMARY_SPI_REGIONID, static_region);
+	u32 count, found;
+	u32 *vbt, *oprom_opreg = NULL;
+	u16 vbt_size, opreg_size;
+	u8 *parse_ptr;
 
-	oprom_offset = I915_READ(OROM_OFFSET);
-	oprom_offset &= OROM_OFFSET_MASK;
+	if (intel_oprom_verify_signature(&oprom_opreg, &opreg_size, dev_priv)) {
+		drm_err(&dev_priv->drm, "oprom signature verification failed\n");
+		goto err_not_found;
+	}
 
-	for (count = 0; count < oprom_size; count += 4) {
-		I915_WRITE(PRIMARY_SPI_ADDRESS, oprom_offset + count);
-		data = I915_READ(PRIMARY_SPI_TRIGGER);
+	if (!oprom_opreg) {
+		drm_err(&dev_priv->drm, "opregion not found\n");
+		goto err_not_found;
+	}
 
-		if (data == *((const u32 *)"$VBT")) {
-			found = oprom_offset + count;
+	for (count = 0; count < opreg_size; count += 4) {
+		if (oprom_opreg[count / 4] == *((const u32 *)"$VBT")) {
+			found = count;
 			break;
 		}
 	}
 
-	if (count >= oprom_size)
+	if (count >= opreg_size) {
+		drm_err(&dev_priv->drm, "VBT not found in opregion\n");
 		goto err_not_found;
+	}
 
 	/* Get VBT size and allocate space for the VBT */
-	I915_WRITE(PRIMARY_SPI_ADDRESS, found +
-		   offsetof(struct vbt_header, vbt_size));
-	vbt_size = I915_READ(PRIMARY_SPI_TRIGGER);
-	vbt_size &= 0xffff;
+	parse_ptr = (u8 *)oprom_opreg + found;
+	vbt_size = ((struct vbt_header *)parse_ptr)->vbt_size;
 
 	vbt = kzalloc(vbt_size, GFP_KERNEL);
 	if (!vbt) {
@@ -2127,16 +2126,12 @@ static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *dev_priv)
 		goto err_not_found;
 	}
 
-	for (count = 0; count < vbt_size; count += 4) {
-		I915_WRITE(PRIMARY_SPI_ADDRESS, found + count);
-		data = I915_READ(PRIMARY_SPI_TRIGGER);
-		*(vbt + store++) = data;
-	}
-
+	memcpy(vbt, parse_ptr, vbt_size);
 	if (!intel_bios_is_valid_vbt(vbt, vbt_size))
 		goto err_free_vbt;
 
 	DRM_DEBUG_KMS("Found valid VBT in SPI flash\n");
+	kfree(oprom_opreg);
 
 	return (struct vbt_header *)vbt;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 4f77cf849171..81e5946393dd 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -983,6 +983,175 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 	return err;
 }
 
+static int oprom_image_parse_helper(u8 *parse_ptr, u8 *last_img, u8 *code_type,
+				    struct drm_i915_private *i915)
+{
+	u8 size_512_bytes;
+
+	if (((union oprom_header *)parse_ptr)->signature != OPROM_IMAGE_MAGIC) {
+		drm_err(&i915->drm, "Wrong OPROM header signature.\n");
+		return -EINVAL;
+	}
+
+	size_512_bytes = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_IMAGE_LENGTH_OFFSET];
+	*code_type = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_CODE_TYPE_OFFSET];
+	*last_img = parse_ptr[((struct expansion_rom_header *)parse_ptr)->pcistructoffset + PCI_LAST_IMAGE_INDICATOR_OFFSET];
+
+	return size_512_bytes;
+}
+
+static void spi_read_oprom_helper(size_t len, u32 offset, u32 *buf,
+				  struct drm_i915_private *dev_priv)
+{
+	u32 count, data;
+
+	for (count = 0; count < len; count += 4) {
+		I915_WRITE(PRIMARY_SPI_ADDRESS, offset + count);
+		data = I915_READ(PRIMARY_SPI_TRIGGER);
+		buf[count / 4] = data;
+	}
+}
+
+/**
+ *	+        DASH+G OPROM IMAGE LAYOUT           +
+ *	+--------+-------+---------------------------+
+ *	| Offset | Value |   ROM Header Fields       +-----> Image 1 (CSS)
+ *	+--------------------------------------------+
+ *	|    0h  |  55h  |   ROM Signature Byte1     |
+ *	|    1h  |  AAh  |   ROM Signature Byte2     |
+ *	|    2h  |  xx   |        Reserved           |
+ *	|  18+19h|  xx   |  Ptr to PCI DataStructure |
+ *	+----------------+---------------------------+
+ *	|           PCI Data Structure               |
+ *	+--------------------------------------------+
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|    10  +  xx   +     Image Length          |
+ *	|    14  +  xx   +     Code Type             |
+ *	|    15  +  xx   +  Last Image Indicator     |
+ *	|    .       .             .                 |
+ *	+--------------------------------------------+
+ *	|               MEU BLOB                     |
+ *	+--------------------------------------------+
+ *	|              CPD Header                    |
+ *	|              CPD Entry                     |
+ *	|              Reserved                      |
+ *	|           SignedDataPart1                  |
+ *	|              PublicKey                     |
+ *	|            RSA Signature                   |
+ *	|           SignedDataPart2                  |
+ *	|            IFWI Metadata                   |
+ *	+--------+-------+---------------------------+
+ *	|    .   |   .   |         .                 |
+ *	|    .   |   .   |         .                 |
+ *	+--------------------------------------------+
+ *	| Offset | Value |   ROM Header Fields       +-----> Image 2 (Config Data) (Offset: 0x800)
+ *	+--------------------------------------------+
+ *	|    0h  |  55h  |   ROM Signature Byte1     |
+ *	|    1h  |  AAh  |   ROM Signature Byte2     |
+ *	|    2h  |  xx   |        Reserved           |
+ *	|  18+19h|  xx   |  Ptr to PCI DataStructure |
+ *	+----------------+---------------------------+
+ *	|           PCI Data Structure               |
+ *	+--------------------------------------------+
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|    10  +  xx   +     Image Length          |
+ *	|    14  +  xx   +      Code Type            |
+ *	|    15  +  xx   +   Last Image Indicator    |
+ *	|    .       .             .                 |
+ *	|    1A  +  3C   + Ptr to Opregion Signature |
+ *	|    .       .             .                 |
+ *	|    .       .             .                 |
+ *	|   83Ch + IntelGraphicsMem                  | <---+ Opregion Signature
+ *	+--------+-----------------------------------+
+ *
+ * intel_oprom_verify_signature() verify OPROM signature.
+ * @opreg: pointer to opregion buffer output.
+ * @opreg_size: pointer to opregion size output.
+ * @dev_priv: i915 device.
+ */
+int
+intel_oprom_verify_signature(u32 **opreg, u16 *opreg_size,
+			     struct drm_i915_private *dev_priv)
+{
+	u8 img_sig[sizeof(OPREGION_SIGNATURE)];
+	u8 code_type, last_img;
+	u32 static_region, offset;
+	u32 *oprom_img, *oprom_img_hdr;
+	u16 opreg_base, img_len;
+	u8 *parse_ptr;
+	int img_size;
+	int ret = -EINVAL;
+
+	/* initialize SPI to read the OPROM */
+	static_region = I915_READ(SPI_STATIC_REGIONS);
+	static_region &= OPTIONROM_SPI_REGIONID_MASK;
+	I915_WRITE(PRIMARY_SPI_REGIONID, static_region);
+	/* read OPROM offset in SPI flash */
+	offset = I915_READ(OROM_OFFSET);
+	offset &= OROM_OFFSET_MASK;
+
+	oprom_img_hdr = kzalloc(OPROM_INITIAL_READ_SIZE, GFP_KERNEL);
+	if (!oprom_img_hdr)
+		return -ENOMEM;
+
+	do {
+		spi_read_oprom_helper(OPROM_INITIAL_READ_SIZE, offset,
+				      oprom_img_hdr, dev_priv);
+		img_size = oprom_image_parse_helper((u8 *)oprom_img_hdr, &last_img,
+						    &code_type, dev_priv);
+		if (img_size <= 0) {
+			ret = -EINVAL;
+			goto err_free_hdr;
+		}
+
+		img_len = img_size * OPROM_BYTE_BOUNDARY;
+		oprom_img = kzalloc(img_len, GFP_KERNEL);
+		if (!oprom_img) {
+			ret = -ENOMEM;
+			goto err_free_hdr;
+		}
+
+		spi_read_oprom_helper(img_len, offset, oprom_img, dev_priv);
+		parse_ptr = (u8 *)oprom_img;
+		offset = offset + img_len;
+
+		/* opregion base offset */
+		opreg_base = ((struct expansion_rom_header *)parse_ptr)->opregion_base;
+		/* CPD or opreg signature is present at opregion_base offset */
+		memcpy(img_sig, parse_ptr + opreg_base, sizeof(OPREGION_SIGNATURE));
+
+		if (!memcmp(img_sig, OPREGION_SIGNATURE, sizeof(OPREGION_SIGNATURE) - 1)) {
+			*opreg = oprom_img;
+			*opreg_size = img_len;
+			drm_dbg_kms(&dev_priv->drm, "Found opregion image\n");
+			ret = 0;
+			break;
+		} else if (!memcmp(img_sig, CPD_SIGNATURE, NUM_CPD_BYTES)) {
+			if (code_type != OPROM_CSS_CODE_TYPE) {
+				drm_err(&dev_priv->drm, "Invalid OPROM\n");
+				ret = -EINVAL;
+				goto err_free_img;
+			}
+			drm_dbg_kms(&dev_priv->drm, "Found CSS image\n");
+			/* proceed here onwards for signature authentication */
+			kfree(oprom_img);
+			continue;
+		}
+
+	} while (last_img != LAST_IMG_INDICATOR);
+
+	return ret;
+
+err_free_img:
+	kfree(oprom_img);
+err_free_hdr:
+	kfree(oprom_img_hdr);
+
+	return ret;
+}
+
 static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id)
 {
 	DRM_INFO("Using panel type from OpRegion on %s\n", id->ident);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 4aa68ffbd30e..4e2eeadf101e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -54,6 +54,34 @@ struct intel_opregion {
 
 #define OPREGION_SIZE            (8 * 1024)
 
+#define CPD_SIGNATURE "$CPD"                  /* CPD Signature */
+#define NUM_CPD_BYTES 4
+#define PCI_IMAGE_LENGTH_OFFSET 0x10
+#define PCI_CODE_TYPE_OFFSET 0x14
+#define PCI_LAST_IMAGE_INDICATOR_OFFSET 0x15
+#define LAST_IMG_INDICATOR 0x80
+#define OPROM_IMAGE_MAGIC 0xAA55       /* Little Endian */
+#define OPROM_CSS_CODE_TYPE 0xF0
+#define OPROM_BYTE_BOUNDARY 512        /* OPROM image sizes are indicated in 512 byte boundaries */
+#define OPROM_INITIAL_READ_SIZE 60     /* Read 60 bytes to compute the Img Len from PCI structure */
+
+union oprom_header {
+	u32 data;
+	struct {
+		u16 signature;  /* Offset[0x0]: Header 0x55 0xAA */
+		u8 sizein512bytes;
+		u8 reserved;
+	};
+};
+
+struct expansion_rom_header {
+	union oprom_header header;      /* Offset[0x0]: Oprom Header */
+	u16 vbiospostoffset;    /* Offset[0x4]: pointer to VBIOS entry point */
+	u8 resvd[0x12];
+	u16 pcistructoffset;    /* Offset[0x18]: Contains pointer PCI Data Structure */
+	u16 opregion_base;      /* Offset[0x1A]: Offset to Opregion Base start */
+};
+
 #ifdef CONFIG_ACPI
 
 int intel_opregion_setup(struct drm_i915_private *dev_priv);
@@ -118,5 +146,6 @@ static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
 }
 
 #endif /* CONFIG_ACPI */
-
+int intel_oprom_verify_signature(u32 **opreg, u16 *opreg_size,
+				 struct drm_i915_private *i915);
 #endif
-- 
2.26.2

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  parent reply	other threads:[~2020-11-27 12:13 UTC|newest]

Thread overview: 420+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-27 12:04 [RFC PATCH 000/162] DG1 + LMEM enabling Matthew Auld
2020-11-27 12:04 ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 001/162] drm/i915/selftest: also consider non-contiguous objects Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 19:44   ` Chris Wilson
2020-11-27 19:44     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:04 ` [RFC PATCH 002/162] drm/i915/selftest: assert we get 2M GTT pages Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 003/162] drm/i915/selftest: handle local-memory in perf_memcpy Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 004/162] drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 19:55   ` Chris Wilson
2020-11-27 19:55     ` Chris Wilson
2020-11-27 12:04 ` [RFC PATCH 005/162] drm/i915/gt: Rename lrc.c to execlists_submission.c Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 19:56   ` Chris Wilson
2020-11-27 19:56     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:04 ` [RFC PATCH 006/162] drm/i915: split gen8+ flush and bb_start emission functions to their own file Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 19:58   ` Chris Wilson
2020-11-27 19:58     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:04 ` [RFC PATCH 007/162] drm/i915: split wa_bb code to its " Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 008/162] HAX drm/i915: Work around the selftest timeline lock splat workaround Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 009/162] drm/i915: Introduce drm_i915_lock_isolated Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 010/162] drm/i915: Lock hwsp objects isolated for pinning at create time Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 011/162] drm/i915: Pin timeline map after first timeline pin, v5 Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 012/162] drm/i915: Move cmd parser pinning to execbuffer Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 013/162] drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2 Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 014/162] drm/i915: Ensure we hold the object mutex in pin correctly v2 Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 015/162] drm/i915: Add gem object locking to madvise Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 016/162] drm/i915: Move HAS_STRUCT_PAGE to obj->flags Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 017/162] drm/i915: Rework struct phys attachment handling Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 018/162] drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2 Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 019/162] drm/i915: make lockdep slightly happier about execbuf Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 020/162] drm/i915: Disable userptr pread/pwrite support Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 021/162] drm/i915: No longer allow exporting userptr through dma-buf Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 022/162] drm/i915: Reject more ioctls for userptr Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:04 ` [RFC PATCH 023/162] drm/i915: Reject UNSYNCHRONIZED for userptr, v2 Matthew Auld
2020-11-27 12:04   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 024/162] drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 025/162] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v5 Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 026/162] drm/i915: Flatten obj->mm.lock Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 027/162] drm/i915: Populate logical context during first pin Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 028/162] drm/i915: Make ring submission compatible with obj->mm.lock removal, v2 Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 029/162] drm/i915: Handle ww locking in init_status_page Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 030/162] drm/i915: Rework clflush to work correctly without obj->mm.lock Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 031/162] drm/i915: Pass ww ctx to intel_pin_to_display_plane Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 032/162] drm/i915: Add object locking to vm_fault_cpu Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 033/162] drm/i915: Move pinning to inside engine_wa_list_verify() Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 034/162] drm/i915: Take reservation lock around i915_vma_pin Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 035/162] drm/i915: Make intel_init_workaround_bb more compatible with ww locking Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 036/162] drm/i915: Make __engine_unpark() compatible with ww locking v2 Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 037/162] drm/i915: Take obj lock around set_domain ioctl Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 038/162] drm/i915: Defer pin calls in buffer pool until first use by caller Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 039/162] drm/i915: Fix pread/pwrite to work with new locking rules Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 040/162] drm/i915: Fix workarounds selftest, part 1 Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 041/162] drm/i915: Prepare for obj->mm.lock removal Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 042/162] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 043/162] drm/i915: Add ww locking around vm_access() Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 044/162] drm/i915: Increase ww locking for perf Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 045/162] drm/i915: Lock ww in ucode objects correctly Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 046/162] drm/i915: Add ww locking to dma-buf ops Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 047/162] drm/i915: Add missing ww lock in intel_dsb_prepare Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 048/162] drm/i915: Fix ww locking in shmem_create_from_object Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 049/162] drm/i915: Use a single page table lock for each gtt Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 050/162] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 051/162] drm/i915/selftests: Prepare client blit " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 052/162] drm/i915/selftests: Prepare coherency tests " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 053/162] drm/i915/selftests: Prepare context " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 054/162] drm/i915/selftests: Prepare dma-buf " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 055/162] drm/i915/selftests: Prepare execbuf " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 056/162] drm/i915/selftests: Prepare mman testcases " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 057/162] drm/i915/selftests: Prepare object tests " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 058/162] drm/i915/selftests: Prepare object blit " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 059/162] drm/i915/selftests: Prepare igt_gem_utils " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 060/162] drm/i915/selftests: Prepare context selftest " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 061/162] drm/i915/selftests: Prepare hangcheck " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 062/162] drm/i915/selftests: Prepare execlists " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 063/162] drm/i915/selftests: Prepare mocs tests " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 064/162] drm/i915/selftests: Prepare ring submission " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 065/162] drm/i915/selftests: Prepare timeline tests " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 066/162] drm/i915/selftests: Prepare i915_request " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 067/162] drm/i915/selftests: Prepare memory region " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 068/162] drm/i915/selftests: Prepare cs engine " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 069/162] drm/i915/selftests: Prepare gtt " Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 070/162] drm/i915: Finally remove obj->mm.lock Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 071/162] drm/i915: Keep userpointer bindings if seqcount is unchanged, v2 Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 072/162] drm/i915: Avoid some false positives in assert_object_held() Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 073/162] drm/i915: Reference contending lock objects Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 074/162] drm/i915: Break out dma_resv ww locking utilities to separate files Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 075/162] drm/i915: Introduce a for_i915_gem_ww(){} Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 076/162] drm/i915: Untangle the vma pages_mutex Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 077/162] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 078/162] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 079/162] drm/i915/dmabuf: Disallow LMEM objects from dma-buf Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 080/162] drm/i915/lmem: Fail driver init if LMEM training failed Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 081/162] HAX drm/i915/lmem: support CPU relocations Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 082/162] HAX drm/i915/lmem: support pread and pwrite Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:05 ` [RFC PATCH 083/162] drm/i915: Update the helper to set correct mapping Matthew Auld
2020-11-27 12:05   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 084/162] drm/i915: introduce kernel blitter_context Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 085/162] drm/i915/region: support basic eviction Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 086/162] drm/i915: Add blit functions that can be called from within a WW transaction Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 087/162] drm/i915: Delay publishing objects on the eviction lists Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 088/162] drm/i915: support basic object migration Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 089/162] drm/i915/dg1: Fix occasional migration error Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 090/162] drm/i915/query: Expose memory regions through the query uAPI Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 091/162] drm/i915: Store gt in memory region Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 092/162] drm/i915/uapi: introduce drm_i915_gem_create_ext Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:25   ` Chris Wilson
2020-11-27 13:25     ` Chris Wilson
2020-12-01 15:06     ` Thomas Hellström (Intel)
2020-12-01 15:06       ` Thomas Hellström (Intel)
2020-11-27 19:21   ` Chris Wilson
2020-11-27 19:21     ` Chris Wilson
2020-12-01 12:55   ` Chris Wilson
2020-12-01 12:55     ` Chris Wilson
2020-12-01 13:43     ` Matthew Auld
2020-12-01 13:43       ` Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 093/162] drm/i915/lmem: allocate cmd ring in lmem Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:27   ` Chris Wilson
2020-11-27 13:27     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 094/162] drm/i915/dg1: Do not check r->sgt.pfn for NULL Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 095/162] drm/i915/dg1: Introduce dmabuf mmap to LMEM Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 096/162] drm/i915: setup the LMEM region Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-30 10:14   ` Jani Nikula
2020-11-30 10:14     ` [Intel-gfx] " Jani Nikula
2020-11-27 12:06 ` [RFC PATCH 097/162] drm/i915: Distinction of memory regions Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:30   ` Chris Wilson
2020-11-27 13:30     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 098/162] drm/i915/gtt: map the PD up front Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:31   ` Chris Wilson
2020-11-27 13:31     ` [Intel-gfx] " Chris Wilson
2021-01-12 10:47     ` Matthew Auld
2021-01-12 10:47       ` Matthew Auld
2021-01-12 14:33       ` Daniel Vetter
2021-01-12 14:33         ` Daniel Vetter
2020-11-27 12:06 ` [RFC PATCH 099/162] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 100/162] drm/i915/gtt: make flushing conditional Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 101/162] drm/i915/gtt/dg1: add PTE_LM plumbing for PPGTT Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:35   ` Chris Wilson
2020-11-27 13:35     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 102/162] drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 103/162] drm/i915: allocate context from LMEM Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:37   ` Chris Wilson
2020-11-27 13:37     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 104/162] drm/i915: move engine scratch to LMEM Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 105/162] drm/i915: Provide a way to disable PCIe relaxed write ordering Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 106/162] drm/i915: i915 returns -EBUSY on thread contention Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 107/162] drm/i915: setup GPU device lmem region Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-30 11:18   ` Chris Wilson
2020-11-30 11:18     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 108/162] drm/i915: Fix object page offset within a region Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 109/162] drm/i915: add i915_gem_object_is_devmem() function Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 110/162] drm/i915: finish memory region support for stolen objects Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 111/162] drm/i915/lmem: support optional CPU clearing for special internal use Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 112/162] drm/i915/guc: put all guc objects in lmem when available Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 113/162] drm/i915: Create stolen memory region from local memory Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-12-07 13:39   ` Jani Nikula
2020-12-07 13:39     ` Jani Nikula
2020-11-27 12:06 ` [RFC PATCH 114/162] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 115/162] drm/i915/lmem: reset the lmem buffer created by fbdev Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 116/162] drm/i915/dsb: Enable lmem for dsb Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 117/162] drm/i915: Reintroduce mem->reserved Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 118/162] drm/i915/dg1: Reserve first 1MB of local memory Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:52   ` Chris Wilson
2020-11-27 13:52     ` Chris Wilson
2020-11-30 11:09     ` Matthew Auld
2020-11-30 11:09       ` Matthew Auld
2020-11-30 11:22       ` Chris Wilson
2020-11-30 11:22         ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 119/162] drm/i915/dg1: Read OPROM via SPI controller Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-30 10:16   ` Jani Nikula
2020-11-30 10:16     ` Jani Nikula
2020-11-27 12:06 ` Matthew Auld [this message]
2020-11-27 12:06   ` [Intel-gfx] [RFC PATCH 120/162] drm/i915/oprom: Basic sanitization Matthew Auld
2020-11-30 10:24   ` Jani Nikula
2020-11-30 10:24     ` Jani Nikula
2020-11-27 12:06 ` [RFC PATCH 121/162] drm/i915: WA for zero memory channel Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 122/162] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 123/162] drm/i915/dg1: Double memory bandwidth available Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 124/162] drm/i915/lmem: allocate HWSP in lmem Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 13:55   ` Chris Wilson
2020-11-27 13:55     ` Chris Wilson
2020-11-30 17:17     ` Matthew Auld
2020-11-30 17:17       ` Matthew Auld
2020-11-30 17:35       ` Chris Wilson
2020-11-30 17:35         ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 125/162] drm/i915/lmem: Limit block size to 4G Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:02   ` Chris Wilson
2020-11-27 14:02     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 126/162] drm/i915/gem: Update shmem available memory Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:04   ` Chris Wilson
2020-11-27 14:04     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 127/162] drm/i915: Allow non-uniform subslices in gen12+ Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 128/162] drm/i915/dg1: intel_memory_region_evict() changes for eviction Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:07   ` Chris Wilson
2020-11-27 14:07     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 129/162] drm/i915/dg1: i915_gem_object_memcpy(..) infrastructure Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 130/162] drm/i915/dg1: Eviction logic Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 131/162] drm/i915/dg1: Add enable_eviction modparam Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-30 12:20   ` Jani Nikula
2020-11-30 12:20     ` [Intel-gfx] " Jani Nikula
2020-11-27 12:06 ` [RFC PATCH 132/162] drm/i915/dg1: Add lmem_size modparam Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 133/162] drm/i915/dg1: Track swap in/out stats via debugfs Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:09   ` Chris Wilson
2020-11-27 14:09     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 134/162] drm/i915/dg1: Measure swap in/out timing stats Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:11   ` Chris Wilson
2020-11-27 14:11     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 135/162] drm/i915: define intel_partial_pages_for_sg_table Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 136/162] drm/i915: create and destroy dummy vma Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 137/162] drm/i915: blt copy between objs using pre-created vma windows Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:19   ` Chris Wilson
2020-11-27 14:19     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 138/162] drm/i915/dg1: Eliminate eviction mutex Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 139/162] drm/i915/dg1: Keep engine awake across whole blit Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 140/162] drm/i915: window_blt_copy is used for swapin and swapout Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:20   ` Chris Wilson
2020-11-27 14:20     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 141/162] drm/i915: Lmem eviction statistics by category Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:21   ` Chris Wilson
2020-11-27 14:21     ` Chris Wilson
2020-11-27 12:06 ` [RFC PATCH 142/162] drm/i915/gem/selftest: test and measure window based blt cpy Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:06 ` [RFC PATCH 143/162] drm/i915: suspend/resume eviction Matthew Auld
2020-11-27 12:06   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:22   ` Chris Wilson
2020-11-27 14:22     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 144/162] drm/i915: Reset blitter context when unpark engine Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:26   ` Chris Wilson
2020-11-27 14:26     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 145/162] drm/i915/dg1: Add dedicated context for blitter eviction Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 146/162] drm/i915/pm: suspend and restore ppgtt mapping Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:29   ` Chris Wilson
2020-11-27 14:29     ` Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 147/162] drm/i915/gt: Allocate default ctx objects in SMEM Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:30   ` Chris Wilson
2020-11-27 14:30     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 148/162] drm/i915: suspend/resume enable blitter eviction Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:32   ` Chris Wilson
2020-11-27 14:32     ` Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 149/162] drm/i915: suspend/resume handling of perma-pinned objects Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 150/162] drm/i915: need consider system BO snoop for dgfx Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:36   ` Chris Wilson
2020-11-27 14:36     ` [Intel-gfx] " Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 151/162] drm/i915: move eviction to prepare hook Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 152/162] drm/i915: Perform execbuffer object locking as a separate step Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 153/162] drm/i915: Implement eviction locking v2 Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 154/162] drm/i915: Support ww eviction Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 155/162] drm/i915: Use a ww transaction in the fault handler Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 156/162] drm/i915: Use a ww transaction in i915_gem_object_pin_map_unlocked() Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 157/162] drm/i915: Improve accuracy of eviction stats Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:40   ` Chris Wilson
2020-11-27 14:40     ` Chris Wilson
2020-11-30 10:36     ` Tvrtko Ursulin
2020-11-30 10:36       ` Tvrtko Ursulin
2020-11-27 12:07 ` [RFC PATCH 158/162] drm/i915: Support ww locks in suspend/resume Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 159/162] drm/i915/dg1: Fix mapping type for default state object Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 160/162] drm/i915/dg1: Fix GPU hang due to shmemfs page drop Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:44   ` Chris Wilson
2020-11-27 14:44     ` Chris Wilson
2020-11-27 12:07 ` [RFC PATCH 161/162] drm/i915/dg1: allow pci to auto probe Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 12:07 ` [RFC PATCH 162/162] drm/i915: drop fake lmem Matthew Auld
2020-11-27 12:07   ` [Intel-gfx] " Matthew Auld
2020-11-27 14:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 + LMEM enabling Patchwork
2020-11-27 14:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-27 15:03 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-11-27 15:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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