From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: swati2.sharma@intel.com, airlied@linux.ie, vandita.kulkarni@intel.com, uma.shankar@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH v3 09/13] drm/i915: Check for FRL training before DP Link training Date: Wed, 2 Dec 2020 19:54:01 +0530 [thread overview] Message-ID: <20201202142405.14951-10-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201202142405.14951-1-ankit.k.nautiyal@intel.com> This patch calls functions to check FRL training requirements for an HDMI2.1 sink, when connected through PCON. The call is made before the DP link training. In case FRL is not required or failure during FRL training, the TMDS mode is selected for the pcon. v2: moved check_frl_training() just after FEC READY, before starting DP link training. v3: rebase Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 76e975b4765b..1c2fdaa4f81a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3651,6 +3651,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + intel_dp_check_frl_training(intel_dp, crtc_state); + /* * 7.i Follow DisplayPort specification training sequence (see notes for * failure handling) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1396ee25812c..58c7e080d918 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4279,6 +4279,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp); + intel_dp_check_frl_training(intel_dp, pipe_config); intel_dp_start_link_train(intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); @@ -6200,6 +6201,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, !intel_dp_mst_is_master_trans(crtc_state)) continue; + intel_dp_check_frl_training(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break; -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 09/13] drm/i915: Check for FRL training before DP Link training Date: Wed, 2 Dec 2020 19:54:01 +0530 [thread overview] Message-ID: <20201202142405.14951-10-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201202142405.14951-1-ankit.k.nautiyal@intel.com> This patch calls functions to check FRL training requirements for an HDMI2.1 sink, when connected through PCON. The call is made before the DP link training. In case FRL is not required or failure during FRL training, the TMDS mode is selected for the pcon. v2: moved check_frl_training() just after FEC READY, before starting DP link training. v3: rebase Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 76e975b4765b..1c2fdaa4f81a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3651,6 +3651,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + intel_dp_check_frl_training(intel_dp, crtc_state); + /* * 7.i Follow DisplayPort specification training sequence (see notes for * failure handling) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1396ee25812c..58c7e080d918 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4279,6 +4279,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp); + intel_dp_check_frl_training(intel_dp, pipe_config); intel_dp_start_link_train(intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); @@ -6200,6 +6201,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, !intel_dp_mst_is_master_trans(crtc_state)) continue; + intel_dp_check_frl_training(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break; -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-02 14:31 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-02 14:23 [PATCH v3 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 03/13] drm/edid: Parse DSC1.2 cap fields " Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 04/13] drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 05/13] drm/dp_helper: Add support for link failure detection Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 06/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 07/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 08/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` Ankit Nautiyal [this message] 2020-12-02 14:24 ` [Intel-gfx] [PATCH v3 09/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 10/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 13/13] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 16:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev5) Patchwork 2020-12-02 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-02 21:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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