From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: swati2.sharma@intel.com, airlied@linux.ie, vandita.kulkarni@intel.com, uma.shankar@intel.com, dri-devel@lists.freedesktop.org Subject: [PATCH v3 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Date: Wed, 2 Dec 2020 19:54:03 +0530 [thread overview] Message-ID: <20201202142405.14951-12-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201202142405.14951-1-ankit.k.nautiyal@intel.com> This patch adds support to read and store the DSC capabilities of the HDMI2.1 PCon encoder. It also adds a new field to store these caps, The caps are read during dfp update and can later be used to get the PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to override the existing PPS-metadata, by either writing the entire new PPS metadata, or by writing only the PPS override parameters. v2: Restructured the code to read all capability DPCDs at once and store in an array in intel_dp structure. v3: rebase Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 997247db499c..604ba249fa51 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1346,6 +1346,7 @@ struct intel_dp { u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable; + u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; /* source rates */ int num_source_rates; const int *source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7d7010b148ec..e3da73499e5a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3980,6 +3980,24 @@ cpt_set_link_train(struct intel_dp *intel_dp, intel_de_posting_read(dev_priv, intel_dp->output_reg); } +static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* Clear the cached register set to avoid using stale values */ + + memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, + intel_dp->pcon_dsc_dpcd, + sizeof(intel_dp->pcon_dsc_dpcd)) < 0) + drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", + DP_PCON_DSC_ENCODER); + + drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", + (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); +} + static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) { int bw_gbps[] = {9, 18, 24, 32, 40, 48}; @@ -6753,6 +6771,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->dfp.max_tmds_clock, intel_dp->dfp.pcon_max_frl_bw, intel_dp->dfp.sink_max_frl_bw); + + intel_dp_get_pcon_dsc_cap(intel_dp); } static void -- 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> To: intel-gfx@lists.freedesktop.org Cc: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Date: Wed, 2 Dec 2020 19:54:03 +0530 [thread overview] Message-ID: <20201202142405.14951-12-ankit.k.nautiyal@intel.com> (raw) In-Reply-To: <20201202142405.14951-1-ankit.k.nautiyal@intel.com> This patch adds support to read and store the DSC capabilities of the HDMI2.1 PCon encoder. It also adds a new field to store these caps, The caps are read during dfp update and can later be used to get the PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to override the existing PPS-metadata, by either writing the entire new PPS metadata, or by writing only the PPS override parameters. v2: Restructured the code to read all capability DPCDs at once and store in an array in intel_dp structure. v3: rebase Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 997247db499c..604ba249fa51 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1346,6 +1346,7 @@ struct intel_dp { u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable; + u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; /* source rates */ int num_source_rates; const int *source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7d7010b148ec..e3da73499e5a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3980,6 +3980,24 @@ cpt_set_link_train(struct intel_dp *intel_dp, intel_de_posting_read(dev_priv, intel_dp->output_reg); } +static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* Clear the cached register set to avoid using stale values */ + + memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, + intel_dp->pcon_dsc_dpcd, + sizeof(intel_dp->pcon_dsc_dpcd)) < 0) + drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", + DP_PCON_DSC_ENCODER); + + drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", + (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); +} + static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) { int bw_gbps[] = {9, 18, 24, 32, 40, 48}; @@ -6753,6 +6771,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->dfp.max_tmds_clock, intel_dp->dfp.pcon_max_frl_bw, intel_dp->dfp.sink_max_frl_bw); + + intel_dp_get_pcon_dsc_cap(intel_dp); } static void -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-02 14:31 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-02 14:23 [PATCH v3 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 03/13] drm/edid: Parse DSC1.2 cap fields " Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 04/13] drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 05/13] drm/dp_helper: Add support for link failure detection Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 06/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:23 ` [PATCH v3 07/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-12-02 14:23 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 08/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 09/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 10/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` Ankit Nautiyal [this message] 2020-12-02 14:24 ` [Intel-gfx] [PATCH v3 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 14:24 ` [PATCH v3 13/13] drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-12-02 14:24 ` [Intel-gfx] " Ankit Nautiyal 2020-12-02 16:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev5) Patchwork 2020-12-02 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-12-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-12-02 21:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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