From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup.patel@wdc.com>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<sagark@eecs.berkeley.edu>, <kbastian@mail.uni-paderborn.de>,
<victor.zhangxiaofeng@huawei.com>, <wu.wubin@huawei.com>,
<zhang.zhanghailiang@huawei.com>, <dengkai1@huawei.com>,
<yinyipeng1@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>
Subject: [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers
Date: Thu, 3 Dec 2020 20:46:52 +0800 [thread overview]
Message-ID: <20201203124703.168-5-jiangyifei@huawei.com> (raw)
In-Reply-To: <20201203124703.168-1-jiangyifei@huawei.com>
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 149 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 86660ba81b..e679619e79 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
return id;
}
+#define RISCV_CORE_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->pc = reg;
+
+ for (i = 1; i < 32; i++) {
+ __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+ ret = kvm_get_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ env->gpr[i] = reg;
+ }
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mstatus = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sie), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mie = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), ®);
+ if (ret) {
+ return ret;
+ }
+ env->stvec = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sscratch = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sepc = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(scause), ®);
+ if (ret) {
+ return ret;
+ }
+ env->scause = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stval), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sbadaddr = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sip), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mip = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(satp), ®);
+ if (ret) {
+ return ret;
+ }
+ env->satp = reg;
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
int kvm_arch_get_registers(CPUState *cs)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_get_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_put_registers(CPUState *cs, int level)
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu,
kvm@vger.kernel.org, libvir-list@redhat.com,
kbastian@mail.uni-paderborn.de, anup.patel@wdc.com,
yinyipeng1@huawei.com, Alistair.Francis@wdc.com,
Yifei Jiang <jiangyifei@huawei.com>,
kvm-riscv@lists.infradead.org, palmer@dabbelt.com,
dengkai1@huawei.com, wu.wubin@huawei.com,
zhang.zhanghailiang@huawei.com
Subject: [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers
Date: Thu, 3 Dec 2020 20:46:52 +0800 [thread overview]
Message-ID: <20201203124703.168-5-jiangyifei@huawei.com> (raw)
In-Reply-To: <20201203124703.168-1-jiangyifei@huawei.com>
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 149 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 86660ba81b..e679619e79 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
return id;
}
+#define RISCV_CORE_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->pc = reg;
+
+ for (i = 1; i < 32; i++) {
+ __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+ ret = kvm_get_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ env->gpr[i] = reg;
+ }
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mstatus = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sie), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mie = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), ®);
+ if (ret) {
+ return ret;
+ }
+ env->stvec = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sscratch = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sepc = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(scause), ®);
+ if (ret) {
+ return ret;
+ }
+ env->scause = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stval), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sbadaddr = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sip), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mip = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(satp), ®);
+ if (ret) {
+ return ret;
+ }
+ env->satp = reg;
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
int kvm_arch_get_registers(CPUState *cs)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_get_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_put_registers(CPUState *cs, int level)
--
2.19.1
next prev parent reply other threads:[~2020-12-03 12:48 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 12:46 [PATCH RFC v4 00/15] Add riscv kvm accel support Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 01/15] linux-header: Update linux/kvm.h Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 02/15] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 03/15] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-08 22:13 ` Alistair Francis
2020-12-08 22:13 ` Alistair Francis
2020-12-03 12:46 ` Yifei Jiang [this message]
2020-12-03 12:46 ` [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 05/15] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-08 22:19 ` Alistair Francis
2020-12-08 22:19 ` Alistair Francis
2020-12-15 7:19 ` Jiangyifei
2020-12-15 7:19 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-08 22:29 ` Alistair Francis
2020-12-08 22:29 ` Alistair Francis
2020-12-15 7:33 ` Jiangyifei
2020-12-15 7:33 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 08/15] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 09/15] target/riscv: Add host cpu type Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-08 22:21 ` Alistair Francis
2020-12-08 22:21 ` Alistair Francis
2020-12-15 7:21 ` Jiangyifei
2020-12-15 7:21 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 11/15] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2020-12-03 12:46 ` Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 12/15] target/riscv: Support virtual time context synchronization Yifei Jiang
2020-12-03 12:47 ` Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine Yifei Jiang
2020-12-03 12:47 ` Yifei Jiang
2020-12-08 22:25 ` Alistair Francis
2020-12-08 22:25 ` Alistair Francis
2020-12-15 7:31 ` Jiangyifei
2020-12-15 7:31 ` Jiangyifei
2021-01-05 17:36 ` Alistair Francis
2021-01-05 17:36 ` Alistair Francis
2020-12-03 12:47 ` [PATCH RFC v4 14/15] target/riscv: Synchronize vcpu's frequency with KVM Yifei Jiang
2020-12-03 12:47 ` Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 15/15] target/riscv: Add time frequency migration support Yifei Jiang
2020-12-03 12:47 ` Yifei Jiang
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