From: Alistair Francis <alistair23@gmail.com> To: Yifei Jiang <jiangyifei@huawei.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "Zhangxiaofeng (F)" <victor.zhangxiaofeng@huawei.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, "open list:Overall" <kvm@vger.kernel.org>, libvir-list@redhat.com, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Anup Patel <anup.patel@wdc.com>, yinyipeng <yinyipeng1@huawei.com>, Alistair Francis <Alistair.Francis@wdc.com>, kvm-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, "dengkai (A)" <dengkai1@huawei.com>, "Wubin (H)" <wu.wubin@huawei.com>, Zhanghailiang <zhang.zhanghailiang@huawei.com> Subject: Re: [PATCH RFC v4 09/15] target/riscv: Add host cpu type Date: Tue, 8 Dec 2020 14:21:55 -0800 [thread overview] Message-ID: <CAKmqyKMDWzBf29MgG7BsGTmweH7ZCRVqwCCqC620QoO776=cww@mail.gmail.com> (raw) In-Reply-To: <20201203124703.168-10-jiangyifei@huawei.com> On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > Currently, host cpu is inherited simply. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> > --- > target/riscv/cpu.c | 6 ++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index faee98a58c..439dc89ee7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -186,6 +186,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > #endif > > +static void riscv_host_cpu_init(Object *obj) > +{ > +} > + > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > { > ObjectClass *oc; > @@ -641,10 +645,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), Shouldn't this only be included if KVM is configured? Also it should be shared between RV32 and RV64. Alistair > #endif > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ad1c90f798..4288898019 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,6 +43,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) > -- > 2.19.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Yifei Jiang <jiangyifei@huawei.com> Cc: kvm-riscv@lists.infradead.org, Anup Patel <anup.patel@wdc.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "open list:Overall" <kvm@vger.kernel.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, libvir-list@redhat.com, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Zhanghailiang <zhang.zhanghailiang@huawei.com>, Alistair Francis <Alistair.Francis@wdc.com>, yinyipeng <yinyipeng1@huawei.com>, Palmer Dabbelt <palmer@dabbelt.com>, "Wubin \(H\)" <wu.wubin@huawei.com>, "dengkai \(A\)" <dengkai1@huawei.com> Subject: Re: [PATCH RFC v4 09/15] target/riscv: Add host cpu type Date: Tue, 8 Dec 2020 14:21:55 -0800 [thread overview] Message-ID: <CAKmqyKMDWzBf29MgG7BsGTmweH7ZCRVqwCCqC620QoO776=cww@mail.gmail.com> (raw) In-Reply-To: <20201203124703.168-10-jiangyifei@huawei.com> On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > Currently, host cpu is inherited simply. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> > --- > target/riscv/cpu.c | 6 ++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index faee98a58c..439dc89ee7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -186,6 +186,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > #endif > > +static void riscv_host_cpu_init(Object *obj) > +{ > +} > + > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > { > ObjectClass *oc; > @@ -641,10 +645,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), Shouldn't this only be included if KVM is configured? Also it should be shared between RV32 and RV64. Alistair > #endif > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ad1c90f798..4288898019 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,6 +43,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) > -- > 2.19.1 > >
next prev parent reply other threads:[~2020-12-08 22:23 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-03 12:46 [PATCH RFC v4 00/15] Add riscv kvm accel support Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 01/15] linux-header: Update linux/kvm.h Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 02/15] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 03/15] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-08 22:13 ` Alistair Francis 2020-12-08 22:13 ` Alistair Francis 2020-12-03 12:46 ` [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 05/15] target/riscv: Implement kvm_arch_put_registers Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-08 22:19 ` Alistair Francis 2020-12-08 22:19 ` Alistair Francis 2020-12-15 7:19 ` Jiangyifei 2020-12-15 7:19 ` Jiangyifei 2020-12-03 12:46 ` [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-08 22:29 ` Alistair Francis 2020-12-08 22:29 ` Alistair Francis 2020-12-15 7:33 ` Jiangyifei 2020-12-15 7:33 ` Jiangyifei 2020-12-03 12:46 ` [PATCH RFC v4 08/15] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 09/15] target/riscv: Add host cpu type Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-08 22:21 ` Alistair Francis [this message] 2020-12-08 22:21 ` Alistair Francis 2020-12-15 7:21 ` Jiangyifei 2020-12-15 7:21 ` Jiangyifei 2020-12-03 12:46 ` [PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:46 ` [PATCH RFC v4 11/15] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang 2020-12-03 12:46 ` Yifei Jiang 2020-12-03 12:47 ` [PATCH RFC v4 12/15] target/riscv: Support virtual time context synchronization Yifei Jiang 2020-12-03 12:47 ` Yifei Jiang 2020-12-03 12:47 ` [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine Yifei Jiang 2020-12-03 12:47 ` Yifei Jiang 2020-12-08 22:25 ` Alistair Francis 2020-12-08 22:25 ` Alistair Francis 2020-12-15 7:31 ` Jiangyifei 2020-12-15 7:31 ` Jiangyifei 2021-01-05 17:36 ` Alistair Francis 2021-01-05 17:36 ` Alistair Francis 2020-12-03 12:47 ` [PATCH RFC v4 14/15] target/riscv: Synchronize vcpu's frequency with KVM Yifei Jiang 2020-12-03 12:47 ` Yifei Jiang 2020-12-03 12:47 ` [PATCH RFC v4 15/15] target/riscv: Add time frequency migration support Yifei Jiang 2020-12-03 12:47 ` Yifei Jiang
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