From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: m.mtretter@pengutronix.de, michals@xilinx.com,
kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org
Subject: [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable
Date: Thu, 21 Jan 2021 08:16:50 +0100 [thread overview]
Message-ID: <20210121071659.1226489-7-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de>
The disabling of the PLL is not fully implemented, because according to
the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
be set to bring the PLL into reset.
Set the bits to disable the PLL.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changelog:
v3: none
v2: none
---
drivers/soc/xilinx/xlnx_vcu.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
index ff66551a5966..34f3299afc0d 100644
--- a/drivers/soc/xilinx/xlnx_vcu.c
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -329,6 +329,10 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
return ret;
}
+ xvcu_write_field_reg(base, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
VCU_PLL_CTRL_POR_IN_SHIFT);
@@ -340,15 +344,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
VCU_PLL_CTRL_PWR_POR_SHIFT;
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_BYPASS_MASK,
- VCU_PLL_CTRL_BYPASS_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 0, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
ret = xvcu_pll_wait_for_lock(xvcu);
if (ret) {
@@ -368,6 +366,18 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
static void xvcu_pll_disable(struct xvcu_device *xvcu)
{
+ void __iomem *base = xvcu->vcu_slcr_ba;
+ u32 vcu_pll_ctrl;
+
+ vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK << VCU_PLL_CTRL_POR_IN_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_POR_IN_MASK) << VCU_PLL_CTRL_POR_IN_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK << VCU_PLL_CTRL_PWR_POR_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_PWR_POR_MASK) << VCU_PLL_CTRL_PWR_POR_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
+
clk_disable_unprepare(xvcu->pll_ref);
}
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: sboyd@kernel.org, mturquette@baylibre.com,
m.mtretter@pengutronix.de, michals@xilinx.com,
kernel@pengutronix.de
Subject: [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable
Date: Thu, 21 Jan 2021 08:16:50 +0100 [thread overview]
Message-ID: <20210121071659.1226489-7-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de>
The disabling of the PLL is not fully implemented, because according to
the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
be set to bring the PLL into reset.
Set the bits to disable the PLL.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changelog:
v3: none
v2: none
---
drivers/soc/xilinx/xlnx_vcu.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
index ff66551a5966..34f3299afc0d 100644
--- a/drivers/soc/xilinx/xlnx_vcu.c
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -329,6 +329,10 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
return ret;
}
+ xvcu_write_field_reg(base, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
VCU_PLL_CTRL_POR_IN_SHIFT);
@@ -340,15 +344,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
VCU_PLL_CTRL_PWR_POR_SHIFT;
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_BYPASS_MASK,
- VCU_PLL_CTRL_BYPASS_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 0, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
ret = xvcu_pll_wait_for_lock(xvcu);
if (ret) {
@@ -368,6 +366,18 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
static void xvcu_pll_disable(struct xvcu_device *xvcu)
{
+ void __iomem *base = xvcu->vcu_slcr_ba;
+ u32 vcu_pll_ctrl;
+
+ vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK << VCU_PLL_CTRL_POR_IN_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_POR_IN_MASK) << VCU_PLL_CTRL_POR_IN_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK << VCU_PLL_CTRL_PWR_POR_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_PWR_POR_MASK) << VCU_PLL_CTRL_PWR_POR_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
+
clk_disable_unprepare(xvcu->pll_ref);
}
--
2.20.1
_______________________________________________
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next prev parent reply other threads:[~2021-01-21 7:19 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 7:16 [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-01-21 7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` Michael Tretter [this message]
2021-01-21 7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter
2021-01-21 7:16 ` Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-02-09 2:35 ` Stephen Boyd
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