From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Date: Thu, 21 Jan 2021 08:16:51 +0100 [thread overview] Message-ID: <20210121071659.1226489-8-m.tretter@pengutronix.de> (raw) In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de> Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is pre-calculated when probing the driver. To still make the clock framework aware of the PLL and to allow to configure other clocks based on the PLL rate, register the PLL as a fixed rate clock. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> --- Changelog: v3: none v2: - Fix kernel-doc of struct xvcu_device - Add missing clk_hw_unregister_fixed_rate --- drivers/soc/xilinx/Kconfig | 2 +- drivers/soc/xilinx/xlnx_vcu.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 0b1708dae361..9fe703772e5a 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -3,7 +3,7 @@ menu "Xilinx SoC drivers" config XILINX_VCU tristate "Xilinx VCU logicoreIP Init" - depends on HAS_IOMEM + depends on HAS_IOMEM && COMMON_CLK select REGMAP_MMIO help Provides the driver to enable and disable the isolation between the diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index 34f3299afc0d..6a733a181982 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -7,6 +7,7 @@ * Contacts Dhaval Shah <dshah@xilinx.com> */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/io.h> @@ -73,6 +74,7 @@ * @aclk: axi clock source * @logicore_reg_ba: logicore reg base address * @vcu_slcr_ba: vcu_slcr Register base address + * @pll: handle for the VCU PLL */ struct xvcu_device { struct device *dev; @@ -80,6 +82,7 @@ struct xvcu_device { struct clk *aclk; struct regmap *logicore_reg_ba; void __iomem *vcu_slcr_ba; + struct clk_hw *pll; }; static struct regmap_config vcu_settings_regmap_config = { @@ -403,7 +406,9 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) u32 clkoutdiv, vcu_pll_ctrl, pll_clk; u32 mod, ctrl; int i; + int ret; const struct xvcu_pll_cfg *found = NULL; + struct clk_hw *hw; regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK, &inte); regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC, &deci); @@ -505,7 +510,18 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl); - return xvcu_pll_set_rate(xvcu, fvco, refclk); + ret = xvcu_pll_set_rate(xvcu, fvco, refclk); + if (ret) + return ret; + + hw = clk_hw_register_fixed_rate(xvcu->dev, "vcu_pll", + __clk_get_name(xvcu->pll_ref), + 0, pll_clk); + if (IS_ERR(hw)) + return PTR_ERR(hw); + xvcu->pll = hw; + + return 0; } /** @@ -652,6 +668,7 @@ static int xvcu_remove(struct platform_device *pdev) /* Add the the Gasket isolation and put the VCU in reset. */ regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); + clk_hw_unregister_fixed_rate(xvcu->pll); xvcu_pll_disable(xvcu); clk_disable_unprepare(xvcu->aclk); -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: sboyd@kernel.org, mturquette@baylibre.com, m.mtretter@pengutronix.de, michals@xilinx.com, kernel@pengutronix.de Subject: [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Date: Thu, 21 Jan 2021 08:16:51 +0100 [thread overview] Message-ID: <20210121071659.1226489-8-m.tretter@pengutronix.de> (raw) In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de> Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is pre-calculated when probing the driver. To still make the clock framework aware of the PLL and to allow to configure other clocks based on the PLL rate, register the PLL as a fixed rate clock. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> --- Changelog: v3: none v2: - Fix kernel-doc of struct xvcu_device - Add missing clk_hw_unregister_fixed_rate --- drivers/soc/xilinx/Kconfig | 2 +- drivers/soc/xilinx/xlnx_vcu.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 0b1708dae361..9fe703772e5a 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -3,7 +3,7 @@ menu "Xilinx SoC drivers" config XILINX_VCU tristate "Xilinx VCU logicoreIP Init" - depends on HAS_IOMEM + depends on HAS_IOMEM && COMMON_CLK select REGMAP_MMIO help Provides the driver to enable and disable the isolation between the diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index 34f3299afc0d..6a733a181982 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -7,6 +7,7 @@ * Contacts Dhaval Shah <dshah@xilinx.com> */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/io.h> @@ -73,6 +74,7 @@ * @aclk: axi clock source * @logicore_reg_ba: logicore reg base address * @vcu_slcr_ba: vcu_slcr Register base address + * @pll: handle for the VCU PLL */ struct xvcu_device { struct device *dev; @@ -80,6 +82,7 @@ struct xvcu_device { struct clk *aclk; struct regmap *logicore_reg_ba; void __iomem *vcu_slcr_ba; + struct clk_hw *pll; }; static struct regmap_config vcu_settings_regmap_config = { @@ -403,7 +406,9 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) u32 clkoutdiv, vcu_pll_ctrl, pll_clk; u32 mod, ctrl; int i; + int ret; const struct xvcu_pll_cfg *found = NULL; + struct clk_hw *hw; regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK, &inte); regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC, &deci); @@ -505,7 +510,18 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl); - return xvcu_pll_set_rate(xvcu, fvco, refclk); + ret = xvcu_pll_set_rate(xvcu, fvco, refclk); + if (ret) + return ret; + + hw = clk_hw_register_fixed_rate(xvcu->dev, "vcu_pll", + __clk_get_name(xvcu->pll_ref), + 0, pll_clk); + if (IS_ERR(hw)) + return PTR_ERR(hw); + xvcu->pll = hw; + + return 0; } /** @@ -652,6 +668,7 @@ static int xvcu_remove(struct platform_device *pdev) /* Add the the Gasket isolation and put the VCU in reset. */ regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); + clk_hw_unregister_fixed_rate(xvcu->pll); xvcu_pll_disable(xvcu); clk_disable_unprepare(xvcu->aclk); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-21 7:43 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-21 7:16 [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-01-21 7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` Michael Tretter [this message] 2021-01-21 7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter 2021-02-09 2:32 ` Stephen Boyd 2021-02-09 2:32 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd 2021-01-21 7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter 2021-01-21 7:16 ` Michael Tretter 2021-02-09 2:35 ` Stephen Boyd 2021-02-09 2:35 ` Stephen Boyd
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