From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function Date: Fri, 26 Feb 2021 11:18:46 +0800 [thread overview] Message-ID: <20210226031902.23656-63-frank.chang@sifive.com> (raw) In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/fpu_helper.c | 5 +++++ target/riscv/helper.h | 1 + target/riscv/internals.h | 1 + target/riscv/translate.c | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index ad84aeebc1c..ac3e7b4d08f 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +void helper_set_rod_rounding_mode(CPURISCVState *env) +{ + set_float_rounding_mode(float_round_to_odd, &env->fp_status); +} + static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e11cce3e8ea..1d52936c399 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 469cc418c4e..6a80c067706 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,6 +43,7 @@ enum { RISCV_FRM_RUP = 3, /* Round Up */ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ + RISCV_FRM_ROD = 8, /* Round to Odd */ }; static inline uint64_t nanbox_s(float32 f) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d9a794d71e8..b9da55c75a8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "instmap.h" +#include "internals.h" /* global register indices */ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; @@ -585,6 +586,10 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } ctx->frm = rm; + if (rm == RISCV_FRM_ROD) { + gen_helper_set_rod_rounding_mode(cpu_env); + return; + } t0 = tcg_const_i32(rm); gen_helper_set_rounding_mode(cpu_env, t0); tcg_temp_free_i32(t0); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function Date: Fri, 26 Feb 2021 11:18:46 +0800 [thread overview] Message-ID: <20210226031902.23656-63-frank.chang@sifive.com> (raw) In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/fpu_helper.c | 5 +++++ target/riscv/helper.h | 1 + target/riscv/internals.h | 1 + target/riscv/translate.c | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index ad84aeebc1c..ac3e7b4d08f 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +void helper_set_rod_rounding_mode(CPURISCVState *env) +{ + set_float_rounding_mode(float_round_to_odd, &env->fp_status); +} + static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e11cce3e8ea..1d52936c399 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 469cc418c4e..6a80c067706 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,6 +43,7 @@ enum { RISCV_FRM_RUP = 3, /* Round Up */ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ + RISCV_FRM_ROD = 8, /* Round to Odd */ }; static inline uint64_t nanbox_s(float32 f) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d9a794d71e8..b9da55c75a8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "instmap.h" +#include "internals.h" /* global register indices */ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; @@ -585,6 +586,10 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } ctx->frm = rm; + if (rm == RISCV_FRM_ROD) { + gen_helper_set_rod_rounding_mode(cpu_env); + return; + } t0 = tcg_const_i32(rm); gen_helper_set_rounding_mode(cpu_env, t0); tcg_temp_free_i32(t0); -- 2.17.1
next prev parent reply other threads:[~2021-02-26 4:23 UTC|newest] Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang 2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` frank.chang [this message] 2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang 2021-02-26 3:18 ` frank.chang
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