From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Hsiangkai Wang <kai.wang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Greentime Hu <greentime.hu@sifive.com> Subject: [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 Date: Fri, 26 Feb 2021 11:18:52 +0800 [thread overview] Message-ID: <20210226031902.23656-69-frank.chang@sifive.com> (raw) In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> From: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d95165b3acb..a110b6ead9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) if (strcmp(xmlname, "riscv-csr.xml") == 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { + return cpu->dyn_vreg_xml; } return NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad2497229db..f324949beb1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,6 +275,7 @@ struct RISCVCPU { CPURISCVState env; char *dyn_csr_xml; + char *dyn_vreg_xml; /* Configuration Settings */ struct { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a9..dd883612c77 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,32 @@ #include "exec/gdbstub.h" #include "cpu.h" +struct TypeSize { + const char *gdb_type; + const char *id; + int size; + const char suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", "quads", 128, 'q' }, + /* 64 bit */ + { "uint64", "longs", 64, 'l' }, + /* 32 bit */ + { "uint32", "words", 32, 'w' }, + /* 16 bit */ + { "uint16", "shorts", 16, 's' }, + /* + * TODO: currently there is no reliable way of telling + * if the remote gdb actually understands ieee_half so + * we don't expose it in the target description for now. + * { "ieee_half", 16, 'h', 'f' }, + */ + /* bytes */ + { "uint8", "bytes", 8, 'b' }, +}; + int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +/* + * Convert register index number passed by GDB to the correspond + * vector CSR number. Vector CSRs are defined after vector registers + * in dynamic generated riscv-vector.xml, thus the starting register index + * of vector CSRs is 32. + * Return 0 if register index number is out of range. + */ +static int riscv_gdb_vector_csrno(int num_regs) +{ + /* + * The order of vector CSRs in the switch case + * should match with the order defined in csr_ops[]. + */ + switch (num_regs) { + case 32: + return CSR_VSTART; + case 33: + return CSR_VXSAT; + case 34: + return CSR_VXRM; + case 35: + return CSR_VCSR; + case 36: + return CSR_VL; + case 37: + return CSR_VTYPE; + case 38: + return CSR_VLENB; + default: + /* Unknown register. */ + return 0; + } +} + +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt = 0; + for (i = 0; i < vlenb; i += 8) { + cnt += gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = 0; + int result = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + if (result == 0) { + return gdb_get_regl(buf, val); + } + + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i = 0; i < vlenb; i += 8) { + env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); + } + return vlenb; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = ldtul_p(mem_buf); + int result = riscv_csrrw_debug(env, csrno, NULL, val, -1); + + if (result == 0) { + return sizeof(target_ulong); + } + + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < CSR_TABLE_SIZE) { @@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) return CSR_TABLE_SIZE; } +static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + GString *s = g_string_new(NULL); + g_autoptr(GString) ts = g_string_new(""); + int reg_width = cpu->cfg.vlen; + int num_regs = 0; + int i; + + g_string_printf(s, "<?xml version=\"1.0\"?>"); + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">"); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "%s", vec_lanes[i].id); + g_string_append_printf(s, + "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", + ts->str, vec_lanes[i].gdb_type, count); + } + + /* Define unions */ + g_string_append_printf(s, "<union id=\"riscv_vector\">"); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>", + vec_lanes[i].suffix, + vec_lanes[i].id); + } + g_string_append(s, "</union>"); + + /* Define vector registers */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "<reg name=\"v%d\" bitsize=\"%d\"" + " regnum=\"%d\" group=\"vector\"" + " type=\"riscv_vector\"/>", + i, reg_width, base_reg++); + num_regs++; + } + + /* Define vector CSRs */ + const char *vector_csrs[7] = { + "vstart", "vxsat", "vxrm", "vcsr", + "vl", "vtype", "vlenb" + }; + + for (i = 0; i < 7; i++) { + g_string_append_printf(s, + "<reg name=\"%s\" bitsize=\"%d\"" + " regnum=\"%d\" group=\"vector\"" + " type=\"int\"/>", + vector_csrs[i], TARGET_LONG_BITS, base_reg++); + num_regs++; + } + + g_string_append_printf(s, "</feature>"); + + cpu->dyn_vreg_xml = g_string_free(s, false); + return num_regs; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa & RVV) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, + ricsv_gen_dynamic_vector_xml(cs, + cs->gdb_num_regs), + "riscv-vector.xml", 0); + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Hsiangkai Wang <kai.wang@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 Date: Fri, 26 Feb 2021 11:18:52 +0800 [thread overview] Message-ID: <20210226031902.23656-69-frank.chang@sifive.com> (raw) In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> From: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d95165b3acb..a110b6ead9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) if (strcmp(xmlname, "riscv-csr.xml") == 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { + return cpu->dyn_vreg_xml; } return NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad2497229db..f324949beb1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,6 +275,7 @@ struct RISCVCPU { CPURISCVState env; char *dyn_csr_xml; + char *dyn_vreg_xml; /* Configuration Settings */ struct { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a9..dd883612c77 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,32 @@ #include "exec/gdbstub.h" #include "cpu.h" +struct TypeSize { + const char *gdb_type; + const char *id; + int size; + const char suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", "quads", 128, 'q' }, + /* 64 bit */ + { "uint64", "longs", 64, 'l' }, + /* 32 bit */ + { "uint32", "words", 32, 'w' }, + /* 16 bit */ + { "uint16", "shorts", 16, 's' }, + /* + * TODO: currently there is no reliable way of telling + * if the remote gdb actually understands ieee_half so + * we don't expose it in the target description for now. + * { "ieee_half", 16, 'h', 'f' }, + */ + /* bytes */ + { "uint8", "bytes", 8, 'b' }, +}; + int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +/* + * Convert register index number passed by GDB to the correspond + * vector CSR number. Vector CSRs are defined after vector registers + * in dynamic generated riscv-vector.xml, thus the starting register index + * of vector CSRs is 32. + * Return 0 if register index number is out of range. + */ +static int riscv_gdb_vector_csrno(int num_regs) +{ + /* + * The order of vector CSRs in the switch case + * should match with the order defined in csr_ops[]. + */ + switch (num_regs) { + case 32: + return CSR_VSTART; + case 33: + return CSR_VXSAT; + case 34: + return CSR_VXRM; + case 35: + return CSR_VCSR; + case 36: + return CSR_VL; + case 37: + return CSR_VTYPE; + case 38: + return CSR_VLENB; + default: + /* Unknown register. */ + return 0; + } +} + +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt = 0; + for (i = 0; i < vlenb; i += 8) { + cnt += gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = 0; + int result = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + if (result == 0) { + return gdb_get_regl(buf, val); + } + + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i = 0; i < vlenb; i += 8) { + env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); + } + return vlenb; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = ldtul_p(mem_buf); + int result = riscv_csrrw_debug(env, csrno, NULL, val, -1); + + if (result == 0) { + return sizeof(target_ulong); + } + + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < CSR_TABLE_SIZE) { @@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) return CSR_TABLE_SIZE; } +static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + GString *s = g_string_new(NULL); + g_autoptr(GString) ts = g_string_new(""); + int reg_width = cpu->cfg.vlen; + int num_regs = 0; + int i; + + g_string_printf(s, "<?xml version=\"1.0\"?>"); + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">"); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "%s", vec_lanes[i].id); + g_string_append_printf(s, + "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", + ts->str, vec_lanes[i].gdb_type, count); + } + + /* Define unions */ + g_string_append_printf(s, "<union id=\"riscv_vector\">"); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>", + vec_lanes[i].suffix, + vec_lanes[i].id); + } + g_string_append(s, "</union>"); + + /* Define vector registers */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "<reg name=\"v%d\" bitsize=\"%d\"" + " regnum=\"%d\" group=\"vector\"" + " type=\"riscv_vector\"/>", + i, reg_width, base_reg++); + num_regs++; + } + + /* Define vector CSRs */ + const char *vector_csrs[7] = { + "vstart", "vxsat", "vxrm", "vcsr", + "vl", "vtype", "vlenb" + }; + + for (i = 0; i < 7; i++) { + g_string_append_printf(s, + "<reg name=\"%s\" bitsize=\"%d\"" + " regnum=\"%d\" group=\"vector\"" + " type=\"int\"/>", + vector_csrs[i], TARGET_LONG_BITS, base_reg++); + num_regs++; + } + + g_string_append_printf(s, "</feature>"); + + cpu->dyn_vreg_xml = g_string_free(s, false); + return num_regs; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa & RVV) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, + ricsv_gen_dynamic_vector_xml(cs, + cs->gdb_num_regs), + "riscv-vector.xml", 0); + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); -- 2.17.1
next prev parent reply other threads:[~2021-02-26 4:06 UTC|newest] Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang 2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang 2021-02-26 3:17 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` frank.chang [this message] 2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang 2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang 2021-02-26 3:18 ` frank.chang 2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang 2021-02-26 3:18 ` frank.chang
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