From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Jonathan Marek <jonathan@marek.ca>, Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Subject: [PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY Date: Wed, 17 Mar 2021 17:40:29 +0300 [thread overview] Message-ID: <20210317144039.556409-17-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20210317144039.556409-1-dmitry.baryshkov@linaro.org> Only 28nm PHY requires sleeping during the VCO rate setting procedure. Rewrite sleeping for 28nm and drop vco_delay from the rest of PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 10 ++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- 4 files changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 81ca0cf2a3ad..7533db8955a5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -96,7 +96,6 @@ struct dsi_pll_10nm { /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -768,8 +767,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll = &pll_10nm->base; pll->cfg = phy->cfg; - pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index c531ddf26521..023727623847 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -122,8 +122,6 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; - int vco_delay; - struct dsi_pll_input in; struct dsi_pll_output out; @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll = &pll_14nm->base; pll->cfg = phy->cfg; - pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index fa96bfc21fdb..e77b21f0d3bf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -69,8 +69,6 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; - int vco_delay; - struct pll_28nm_cached_state cached_state; }; @@ -209,8 +207,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); /* Add hardware recommended delay for correct PLL configuration */ - if (pll_28nm->vco_delay) - udelay(pll_28nm->vco_delay); + if (pll->cfg->type == MSM_DSI_PHY_28NM_HPM) + udelay(1); + else /* LP */ + udelay(1000); pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); @@ -576,7 +576,6 @@ static int dsi_pll_28nm_hpm_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll_28nm->vco_delay = 1; pll->cfg = phy->cfg; @@ -616,7 +615,6 @@ static int dsi_pll_28nm_lp_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll_28nm->vco_delay = 1000; pll->cfg = phy->cfg; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c6f0aca66fa9..d3fea4a2b498 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -96,7 +96,6 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -793,8 +792,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->cfg = phy->cfg; - pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Jonathan Marek <jonathan@marek.ca>, Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Subject: [PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY Date: Wed, 17 Mar 2021 17:40:29 +0300 [thread overview] Message-ID: <20210317144039.556409-17-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20210317144039.556409-1-dmitry.baryshkov@linaro.org> Only 28nm PHY requires sleeping during the VCO rate setting procedure. Rewrite sleeping for 28nm and drop vco_delay from the rest of PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 10 ++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- 4 files changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 81ca0cf2a3ad..7533db8955a5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -96,7 +96,6 @@ struct dsi_pll_10nm { /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -768,8 +767,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll = &pll_10nm->base; pll->cfg = phy->cfg; - pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index c531ddf26521..023727623847 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -122,8 +122,6 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; - int vco_delay; - struct dsi_pll_input in; struct dsi_pll_output out; @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll = &pll_14nm->base; pll->cfg = phy->cfg; - pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index fa96bfc21fdb..e77b21f0d3bf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -69,8 +69,6 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; - int vco_delay; - struct pll_28nm_cached_state cached_state; }; @@ -209,8 +207,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); /* Add hardware recommended delay for correct PLL configuration */ - if (pll_28nm->vco_delay) - udelay(pll_28nm->vco_delay); + if (pll->cfg->type == MSM_DSI_PHY_28NM_HPM) + udelay(1); + else /* LP */ + udelay(1000); pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); @@ -576,7 +576,6 @@ static int dsi_pll_28nm_hpm_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll_28nm->vco_delay = 1; pll->cfg = phy->cfg; @@ -616,7 +615,6 @@ static int dsi_pll_28nm_lp_init(struct msm_dsi_phy *phy) } pll = &pll_28nm->base; - pll_28nm->vco_delay = 1000; pll->cfg = phy->cfg; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c6f0aca66fa9..d3fea4a2b498 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -96,7 +96,6 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -793,8 +792,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->cfg = phy->cfg; - pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); -- 2.30.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-03-17 14:42 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-17 14:40 [PATCH v1 00/26] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 01/26] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 02/26] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 03/26] drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* code Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 04/26] drm/msm/dsi: drop multiple pll enable_seq support Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 05/26] drm/msm/dsi: move all PLL callbacks into PHY config struct Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 06/26] drm/msm/dsi: move min/max PLL rate to phy config Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 07/26] drm/msm/dsi: remove msm_dsi_pll_set_usecase Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 08/26] drm/msm/dsi: stop setting clock parents manually Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 09/26] arm64: dts: qcom: sm8250: assign DSI clock source parents Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 10/26] arm64: dts: qcom: sdm845: " Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 11/26] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 12/26] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 13/26] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 14/26] drm/msm/dsi: replace PHY's init callback with configurable data Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 15/26] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov [this message] 2021-03-17 14:40 ` [PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 17/26] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 18/26] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 19/26] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 20/26] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 21/26] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 22/26] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 23/26] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 24/26] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 25/26] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov 2021-03-17 14:40 ` [PATCH v1 26/26] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov 2021-03-17 14:40 ` Dmitry Baryshkov
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