From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Jonathan Marek <jonathan@marek.ca>,
Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org
Subject: [PATCH v1 17/26] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare
Date: Wed, 17 Mar 2021 17:40:30 +0300 [thread overview]
Message-ID: <20210317144039.556409-18-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20210317144039.556409-1-dmitry.baryshkov@linaro.org>
10nm and 7nm already do not use these helpers, as they handle setting
slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
remove unnecessary indirection and drop enable_seq/disable_seq PLL
callbacks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 87 +++++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 88 ++++++++-----
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 120 ++++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 35 -----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 2 -
6 files changed, 170 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 75fc24f9f013..0fff9e3afb53 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -35,8 +35,6 @@ struct msm_dsi_phy_ops {
};
struct msm_dsi_pll_ops {
- int (*enable_seq)(struct msm_dsi_pll *pll);
- void (*disable_seq)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 023727623847..23f198164c0e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -652,12 +652,58 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
return (unsigned long)vco_rate;
}
+static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *base = pll_14nm->mmio;
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ bool locked;
+
+ DBG("");
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
+
+ locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
+ POLL_TIMEOUT_US);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+
+ DBG("");
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_14nm_vco_set_rate,
.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_14nm_vco_prepare,
+ .unprepare = dsi_pll_14nm_vco_unprepare,
};
/*
@@ -749,39 +795,6 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
* PLL Callbacks
*/
-static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *base = pll_14nm->mmio;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
- bool locked;
-
- DBG("");
-
- pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
-
- locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
- POLL_TIMEOUT_US);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
-
- DBG("");
-
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
-}
-
static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
@@ -1158,8 +1171,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -1185,8 +1196,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index e77b21f0d3bf..5188ba21afa7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -286,19 +286,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
-static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
- .set_rate = dsi_pll_28nm_clk_set_rate,
- .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
- .is_enabled = dsi_pll_28nm_clk_is_enabled,
-};
-
-/*
- * PLL Callbacks
- */
-static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
@@ -373,21 +361,28 @@ static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
return locked ? 0 : -EINVAL;
}
-static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
int i, ret;
+ if (unlikely(pll->pll_on))
+ return 0;
+
for (i = 0; i < 3; i++) {
- ret = _dsi_pll_28nm_enable_seq_hpm(pll);
- if (!ret)
+ ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
+ if (!ret) {
+ pll->pll_on = true;
return 0;
+ }
}
return ret;
}
-static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
@@ -397,6 +392,9 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
DBG("id=%d", pll_28nm->id);
+ if (unlikely(pll->pll_on))
+ return 0;
+
pll_28nm_software_reset(pll_28nm);
/*
@@ -421,22 +419,54 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
- if (unlikely(!locked))
+ if (unlikely(!locked)) {
DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
+ return -EINVAL;
+ }
- return locked ? 0 : -EINVAL;
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
}
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
+
+ pll->pll_on = false;
}
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_hpm,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_lp,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+/*
+ * PLL Callbacks
+ */
+
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -479,7 +509,7 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecell_data *provided_clocks)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecell_data *provided_clocks, const struct clk_ops *vco_ops)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
@@ -487,7 +517,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecel
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
- .ops = &clk_ops_dsi_pll_28nm_vco,
+ .ops = vco_ops,
};
struct device *dev = &pll_28nm->pdev->dev;
struct clk_hw *hw;
@@ -579,7 +609,7 @@ static int dsi_pll_28nm_hpm_init(struct msm_dsi_phy *phy)
pll->cfg = phy->cfg;
- ret = pll_28nm_register(pll_28nm, phy->provided_clocks);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks, &clk_ops_dsi_pll_28nm_vco_hpm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -618,7 +648,7 @@ static int dsi_pll_28nm_lp_init(struct msm_dsi_phy *phy)
pll->cfg = phy->cfg;
- ret = pll_28nm_register(pll_28nm, phy->provided_clocks);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks, &clk_ops_dsi_pll_28nm_vco_lp);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -792,8 +822,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -819,8 +847,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -846,8 +872,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_lp,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 558d311b13a9..15b05ae554a0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -178,12 +178,76 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
+static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct device *dev = &pll_28nm->pdev->dev;
+ void __iomem *base = pll_28nm->mmio;
+ bool locked;
+ unsigned int bit_div, byte_div;
+ int max_reads = 1000, timeout_us = 100;
+ u32 val;
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ /*
+ * before enabling the PLL, configure the bit clock divider since we
+ * don't expose it as a clock to the outside world
+ * 1: read back the byte clock divider that should already be set
+ * 2: divide by 8 to get bit clock divider
+ * 3: write it to POSTDIV1
+ */
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ byte_div = val + 1;
+ bit_div = byte_div / 8;
+
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val &= ~0xf;
+ val |= (bit_div - 1);
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
+
+ /* enable the PLL */
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
+ DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
+
+ locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_28nm_vco_prepare,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
.is_enabled = dsi_pll_28nm_clk_is_enabled,
};
@@ -270,56 +334,6 @@ static const struct clk_ops clk_bytediv_ops = {
/*
* PLL Callbacks
*/
-static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
- struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
- bool locked;
- unsigned int bit_div, byte_div;
- int max_reads = 1000, timeout_us = 100;
- u32 val;
-
- DBG("id=%d", pll_28nm->id);
-
- /*
- * before enabling the PLL, configure the bit clock divider since we
- * don't expose it as a clock to the outside world
- * 1: read back the byte clock divider that should already be set
- * 2: divide by 8 to get bit clock divider
- * 3: write it to POSTDIV1
- */
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
- byte_div = val + 1;
- bit_div = byte_div / 8;
-
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
- val &= ~0xf;
- val |= (bit_div - 1);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
-
- /* enable the PLL */
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
- DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
-
- locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- DBG("id=%d", pll_28nm->id);
- pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
-}
-
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -653,8 +667,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 652c2d6bfeec..cae668b669a4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -21,38 +21,3 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
else
return rate;
}
-
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- int ret = 0;
-
- /*
- * Certain PLLs do not allow VCO rate update when it is on.
- * Keep track of their status to turn on/off after set rate success.
- */
- if (unlikely(pll->pll_on))
- return 0;
-
- ret = pll->cfg->pll_ops.enable_seq(pll);
- if (ret) {
- DRM_ERROR("DSI PLL failed to lock\n");
- return ret;
- }
-
- pll->pll_on = true;
-
- return 0;
-}
-
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-
- if (unlikely(!pll->pll_on))
- return;
-
- pll->cfg->pll_ops.disable_seq(pll);
-
- pll->pll_on = false;
-}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index eca13cf67c21..da83e4c11f4f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -39,8 +39,6 @@ static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
/* clock callbacks */
long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate);
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
#endif /* __DSI_PLL_H__ */
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Jonathan Marek <jonathan@marek.ca>,
Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org
Subject: [PATCH v1 17/26] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare
Date: Wed, 17 Mar 2021 17:40:30 +0300 [thread overview]
Message-ID: <20210317144039.556409-18-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20210317144039.556409-1-dmitry.baryshkov@linaro.org>
10nm and 7nm already do not use these helpers, as they handle setting
slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
remove unnecessary indirection and drop enable_seq/disable_seq PLL
callbacks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 87 +++++++------
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 88 ++++++++-----
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 120 ++++++++++--------
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c | 35 -----
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h | 2 -
6 files changed, 170 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 75fc24f9f013..0fff9e3afb53 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -35,8 +35,6 @@ struct msm_dsi_phy_ops {
};
struct msm_dsi_pll_ops {
- int (*enable_seq)(struct msm_dsi_pll *pll);
- void (*disable_seq)(struct msm_dsi_pll *pll);
void (*save_state)(struct msm_dsi_pll *pll);
int (*restore_state)(struct msm_dsi_pll *pll);
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 023727623847..23f198164c0e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -652,12 +652,58 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
return (unsigned long)vco_rate;
}
+static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *base = pll_14nm->mmio;
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+ bool locked;
+
+ DBG("");
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
+
+ locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
+ POLL_TIMEOUT_US);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
+ void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
+
+ DBG("");
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_14nm_vco_set_rate,
.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_14nm_vco_prepare,
+ .unprepare = dsi_pll_14nm_vco_unprepare,
};
/*
@@ -749,39 +795,6 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
* PLL Callbacks
*/
-static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *base = pll_14nm->mmio;
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
- bool locked;
-
- DBG("");
-
- pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
-
- locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
- POLL_TIMEOUT_US);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
- void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
-
- DBG("");
-
- pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
-}
-
static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
@@ -1158,8 +1171,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -1185,8 +1196,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.pll_ops = {
.save_state = dsi_pll_14nm_save_state,
.restore_state = dsi_pll_14nm_restore_state,
- .disable_seq = dsi_pll_14nm_disable_seq,
- .enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index e77b21f0d3bf..5188ba21afa7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -286,19 +286,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
-static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
- .round_rate = msm_dsi_pll_helper_clk_round_rate,
- .set_rate = dsi_pll_28nm_clk_set_rate,
- .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
- .is_enabled = dsi_pll_28nm_clk_is_enabled,
-};
-
-/*
- * PLL Callbacks
- */
-static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int _dsi_pll_28nm_vco_prepare_hpm(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
@@ -373,21 +361,28 @@ static int _dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
return locked ? 0 : -EINVAL;
}
-static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
int i, ret;
+ if (unlikely(pll->pll_on))
+ return 0;
+
for (i = 0; i < 3; i++) {
- ret = _dsi_pll_28nm_enable_seq_hpm(pll);
- if (!ret)
+ ret = _dsi_pll_28nm_vco_prepare_hpm(pll);
+ if (!ret) {
+ pll->pll_on = true;
return 0;
+ }
}
return ret;
}
-static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
+static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
@@ -397,6 +392,9 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
DBG("id=%d", pll_28nm->id);
+ if (unlikely(pll->pll_on))
+ return 0;
+
pll_28nm_software_reset(pll_28nm);
/*
@@ -421,22 +419,54 @@ static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
- if (unlikely(!locked))
+ if (unlikely(!locked)) {
DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
+ return -EINVAL;
+ }
- return locked ? 0 : -EINVAL;
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
}
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
+
+ pll->pll_on = false;
}
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_hpm,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = {
+ .round_rate = msm_dsi_pll_helper_clk_round_rate,
+ .set_rate = dsi_pll_28nm_clk_set_rate,
+ .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
+ .prepare = dsi_pll_28nm_vco_prepare_lp,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
+ .is_enabled = dsi_pll_28nm_clk_is_enabled,
+};
+
+/*
+ * PLL Callbacks
+ */
+
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -479,7 +509,7 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
return 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecell_data *provided_clocks)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecell_data *provided_clocks, const struct clk_ops *vco_ops)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
@@ -487,7 +517,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw_onecel
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
- .ops = &clk_ops_dsi_pll_28nm_vco,
+ .ops = vco_ops,
};
struct device *dev = &pll_28nm->pdev->dev;
struct clk_hw *hw;
@@ -579,7 +609,7 @@ static int dsi_pll_28nm_hpm_init(struct msm_dsi_phy *phy)
pll->cfg = phy->cfg;
- ret = pll_28nm_register(pll_28nm, phy->provided_clocks);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks, &clk_ops_dsi_pll_28nm_vco_hpm);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -618,7 +648,7 @@ static int dsi_pll_28nm_lp_init(struct msm_dsi_phy *phy)
pll->cfg = phy->cfg;
- ret = pll_28nm_register(pll_28nm, phy->provided_clocks);
+ ret = pll_28nm_register(pll_28nm, phy->provided_clocks, &clk_ops_dsi_pll_28nm_vco_lp);
if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
return ret;
@@ -792,8 +822,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -819,8 +847,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
@@ -846,8 +872,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq_lp,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 558d311b13a9..15b05ae554a0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -178,12 +178,76 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
return vco_rate;
}
+static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+ struct device *dev = &pll_28nm->pdev->dev;
+ void __iomem *base = pll_28nm->mmio;
+ bool locked;
+ unsigned int bit_div, byte_div;
+ int max_reads = 1000, timeout_us = 100;
+ u32 val;
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(pll->pll_on))
+ return 0;
+
+ /*
+ * before enabling the PLL, configure the bit clock divider since we
+ * don't expose it as a clock to the outside world
+ * 1: read back the byte clock divider that should already be set
+ * 2: divide by 8 to get bit clock divider
+ * 3: write it to POSTDIV1
+ */
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ byte_div = val + 1;
+ bit_div = byte_div / 8;
+
+ val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val &= ~0xf;
+ val |= (bit_div - 1);
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
+
+ /* enable the PLL */
+ pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
+ DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
+
+ locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
+
+ if (unlikely(!locked)) {
+ DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
+ return -EINVAL;
+ }
+
+ DBG("DSI PLL lock success");
+ pll->pll_on = true;
+
+ return 0;
+}
+
+static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
+{
+ struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
+ struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
+
+ DBG("id=%d", pll_28nm->id);
+
+ if (unlikely(!pll->pll_on))
+ return;
+
+ pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
+
+ pll->pll_on = false;
+}
+
static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
.round_rate = msm_dsi_pll_helper_clk_round_rate,
.set_rate = dsi_pll_28nm_clk_set_rate,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
- .prepare = msm_dsi_pll_helper_clk_prepare,
- .unprepare = msm_dsi_pll_helper_clk_unprepare,
+ .prepare = dsi_pll_28nm_vco_prepare,
+ .unprepare = dsi_pll_28nm_vco_unprepare,
.is_enabled = dsi_pll_28nm_clk_is_enabled,
};
@@ -270,56 +334,6 @@ static const struct clk_ops clk_bytediv_ops = {
/*
* PLL Callbacks
*/
-static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
- struct device *dev = &pll_28nm->pdev->dev;
- void __iomem *base = pll_28nm->mmio;
- bool locked;
- unsigned int bit_div, byte_div;
- int max_reads = 1000, timeout_us = 100;
- u32 val;
-
- DBG("id=%d", pll_28nm->id);
-
- /*
- * before enabling the PLL, configure the bit clock divider since we
- * don't expose it as a clock to the outside world
- * 1: read back the byte clock divider that should already be set
- * 2: divide by 8 to get bit clock divider
- * 3: write it to POSTDIV1
- */
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
- byte_div = val + 1;
- bit_div = byte_div / 8;
-
- val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
- val &= ~0xf;
- val |= (bit_div - 1);
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
-
- /* enable the PLL */
- pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
- DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
-
- locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
-
- if (unlikely(!locked))
- DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
- else
- DBG("DSI PLL lock success");
-
- return locked ? 0 : -EINVAL;
-}
-
-static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- DBG("id=%d", pll_28nm->id);
- pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
-}
-
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
{
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
@@ -653,8 +667,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.pll_ops = {
.save_state = dsi_pll_28nm_save_state,
.restore_state = dsi_pll_28nm_restore_state,
- .disable_seq = dsi_pll_28nm_disable_seq,
- .enable_seq = dsi_pll_28nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index 652c2d6bfeec..cae668b669a4 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -21,38 +21,3 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
else
return rate;
}
-
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- int ret = 0;
-
- /*
- * Certain PLLs do not allow VCO rate update when it is on.
- * Keep track of their status to turn on/off after set rate success.
- */
- if (unlikely(pll->pll_on))
- return 0;
-
- ret = pll->cfg->pll_ops.enable_seq(pll);
- if (ret) {
- DRM_ERROR("DSI PLL failed to lock\n");
- return ret;
- }
-
- pll->pll_on = true;
-
- return 0;
-}
-
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-
- if (unlikely(!pll->pll_on))
- return;
-
- pll->cfg->pll_ops.disable_seq(pll);
-
- pll->pll_on = false;
-}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index eca13cf67c21..da83e4c11f4f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -39,8 +39,6 @@ static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
/* clock callbacks */
long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate);
-int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
-void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
#endif /* __DSI_PLL_H__ */
--
2.30.2
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next prev parent reply other threads:[~2021-03-17 14:42 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 14:40 [PATCH v1 00/26] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 01/26] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 02/26] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 03/26] drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* code Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 04/26] drm/msm/dsi: drop multiple pll enable_seq support Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 05/26] drm/msm/dsi: move all PLL callbacks into PHY config struct Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 06/26] drm/msm/dsi: move min/max PLL rate to phy config Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 07/26] drm/msm/dsi: remove msm_dsi_pll_set_usecase Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 08/26] drm/msm/dsi: stop setting clock parents manually Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 09/26] arm64: dts: qcom: sm8250: assign DSI clock source parents Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 10/26] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 11/26] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 12/26] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 13/26] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 14/26] drm/msm/dsi: replace PHY's init callback with configurable data Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 15/26] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov [this message]
2021-03-17 14:40 ` [PATCH v1 17/26] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 18/26] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 19/26] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 20/26] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 21/26] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 22/26] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 23/26] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 24/26] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 25/26] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
2021-03-17 14:40 ` [PATCH v1 26/26] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov
2021-03-17 14:40 ` Dmitry Baryshkov
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