From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [RESEND PATCH v7 13/22] clk: mediatek: Add MT8192 imgsys clock support Date: Wed, 24 Mar 2021 18:41:01 +0800 [thread overview] Message-ID: <20210324104110.13383-14-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210324104110.13383-1-chun-jie.chen@mediatek.com> Add MT8192 imgsys and imgsys2 clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-img.c | 70 +++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index a39a4c201c9e..38011dccfe47 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -520,6 +520,12 @@ config COMMON_CLK_MT8192_CAMSYS help This driver supports MediaTek MT8192 camsys and camsys_raw clocks. +config COMMON_CLK_MT8192_IMGSYS + bool "Clock driver for MediaTek MT8192 imgsys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 imgsys and imgsys2 clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 94bf7a03fd88..91392cb333fd 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -70,5 +70,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o +obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c new file mode 100644 index 000000000000..24b414386369 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0), + GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1), + GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2), + GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12), +}; + +static const struct mtk_gate img2_clks[] = { + GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0), + GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1), + GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6), + GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7), + GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8), + GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12), +}; + +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; + +static const struct mtk_clk_desc img2_desc = { + .clks = img2_clks, + .num_clks = ARRAY_SIZE(img2_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_img[] = { + { + .compatible = "mediatek,mt8192-imgsys", + .data = &img_desc, + }, { + .compatible = "mediatek,mt8192-imgsys2", + .data = &img2_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_img_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-img", + .of_match_table = of_match_clk_mt8192_img, + }, +}; + +builtin_platform_driver(clk_mt8192_img_drv); -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [RESEND PATCH v7 13/22] clk: mediatek: Add MT8192 imgsys clock support Date: Wed, 24 Mar 2021 18:41:01 +0800 [thread overview] Message-ID: <20210324104110.13383-14-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210324104110.13383-1-chun-jie.chen@mediatek.com> Add MT8192 imgsys and imgsys2 clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-img.c | 70 +++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index a39a4c201c9e..38011dccfe47 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -520,6 +520,12 @@ config COMMON_CLK_MT8192_CAMSYS help This driver supports MediaTek MT8192 camsys and camsys_raw clocks. +config COMMON_CLK_MT8192_IMGSYS + bool "Clock driver for MediaTek MT8192 imgsys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 imgsys and imgsys2 clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 94bf7a03fd88..91392cb333fd 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -70,5 +70,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o +obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c new file mode 100644 index 000000000000..24b414386369 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0), + GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1), + GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2), + GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12), +}; + +static const struct mtk_gate img2_clks[] = { + GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0), + GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1), + GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6), + GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7), + GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8), + GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12), +}; + +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; + +static const struct mtk_clk_desc img2_desc = { + .clks = img2_clks, + .num_clks = ARRAY_SIZE(img2_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_img[] = { + { + .compatible = "mediatek,mt8192-imgsys", + .data = &img_desc, + }, { + .compatible = "mediatek,mt8192-imgsys2", + .data = &img2_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_img_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-img", + .of_match_table = of_match_clk_mt8192_img, + }, +}; + +builtin_platform_driver(clk_mt8192_img_drv); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-03-24 10:52 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-24 10:40 [RESEND PATCH v7 00/22] Mediatek MT8192 clock support chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-04-30 1:42 ` Stephen Boyd 2021-04-30 1:42 ` Stephen Boyd 2021-05-05 11:23 ` Chun-Jie Chen 2021-05-05 11:23 ` Chun-Jie Chen 2021-03-24 10:40 ` [RESEND PATCH v7 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 10/22] clk: mediatek: Add MT8192 basic clocks support chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:40 ` [RESEND PATCH v7 11/22] clk: mediatek: Add MT8192 audio clock support chun-jie.chen 2021-03-24 10:40 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 12/22] clk: mediatek: Add MT8192 camsys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen [this message] 2021-03-24 10:41 ` [RESEND PATCH v7 13/22] clk: mediatek: Add MT8192 imgsys " chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 15/22] clk: mediatek: Add MT8192 ipesys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 16/22] clk: mediatek: Add MT8192 mdpsys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 17/22] clk: mediatek: Add MT8192 mfgcfg " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 18/22] clk: mediatek: Add MT8192 mmsys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 19/22] clk: mediatek: Add MT8192 msdc " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 20/22] clk: mediatek: Add MT8192 scp adsp " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 21/22] clk: mediatek: Add MT8192 vdecsys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-03-24 10:41 ` [RESEND PATCH v7 22/22] clk: mediatek: Add MT8192 vencsys " chun-jie.chen 2021-03-24 10:41 ` chun-jie.chen 2021-04-08 11:28 ` [RESEND PATCH v7 00/22] Mediatek MT8192 " 20181221120906 created 2021-04-08 11:28 ` 20181221120906 created 2021-04-28 6:44 ` Ikjoon Jang 2021-04-28 6:44 ` Ikjoon Jang 2021-04-28 6:44 ` Ikjoon Jang 2021-05-05 6:58 ` Chun-Jie Chen 2021-05-05 6:58 ` Chun-Jie Chen
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