From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linux-mm@kvack.org, akpm@linux-foundation.org Cc: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, kaleshsingh@google.com, npiggin@gmail.com, joel@joelfernandes.org, Christophe Leroy <christophe.leroy@csgroup.eu>, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Subject: [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Date: Thu, 22 Apr 2021 11:13:18 +0530 [thread overview] Message-ID: <20210422054323.150993-5-aneesh.kumar@linux.ibm.com> (raw) In-Reply-To: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com> Update _tlbiel_pid() such that we can avoid build errors like below when using this function in other places. arch/powerpc/mm/book3s64/radix_tlb.c: In function ‘__radix__flush_tlb_range_psize’: arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably does not match constraints 114 | asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) | ^~~ arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constraint in ‘asm’ make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radix_tlb.o] Error 1 m With this fix, we can also drop the __always_inline in __radix_flush_tlb_range_psize which was added by commit e12d6d7d46a6 ("powerpc/mm/radix: mark __radix__flush_tlb_range_psize() as __always_inline") Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- arch/powerpc/mm/book3s64/radix_tlb.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index 409e61210789..817a02ef6032 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -291,22 +291,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) /* * We use 128 set in radix mode and 256 set in hpt mode. */ -static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) +static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) { int set; asm volatile("ptesync": : :"memory"); - /* - * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL, - * also flush the entire Page Walk Cache. - */ - __tlbiel_pid(pid, 0, ric); + switch (ric) { + case RIC_FLUSH_PWC: - /* For PWC, only one flush is needed */ - if (ric == RIC_FLUSH_PWC) { + /* For PWC, only one flush is needed */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); ppc_after_tlbiel_barrier(); return; + case RIC_FLUSH_TLB: + __tlbiel_pid(pid, 0, RIC_FLUSH_TLB); + break; + case RIC_FLUSH_ALL: + default: + /* + * Flush the first set of the TLB, and if + * we're doing a RIC_FLUSH_ALL, also flush + * the entire Page Walk Cache. + */ + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); } if (!cpu_has_feature(CPU_FTR_ARCH_31)) { @@ -1176,7 +1184,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) } } -static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, +static void __radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, unsigned long end, int psize, bool also_pwc) { -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linux-mm@kvack.org, akpm@linux-foundation.org Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>, npiggin@gmail.com, kaleshsingh@google.com, joel@joelfernandes.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Date: Thu, 22 Apr 2021 11:13:18 +0530 [thread overview] Message-ID: <20210422054323.150993-5-aneesh.kumar@linux.ibm.com> (raw) In-Reply-To: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com> Update _tlbiel_pid() such that we can avoid build errors like below when using this function in other places. arch/powerpc/mm/book3s64/radix_tlb.c: In function ‘__radix__flush_tlb_range_psize’: arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably does not match constraints 114 | asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) | ^~~ arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constraint in ‘asm’ make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radix_tlb.o] Error 1 m With this fix, we can also drop the __always_inline in __radix_flush_tlb_range_psize which was added by commit e12d6d7d46a6 ("powerpc/mm/radix: mark __radix__flush_tlb_range_psize() as __always_inline") Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- arch/powerpc/mm/book3s64/radix_tlb.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index 409e61210789..817a02ef6032 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -291,22 +291,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) /* * We use 128 set in radix mode and 256 set in hpt mode. */ -static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) +static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) { int set; asm volatile("ptesync": : :"memory"); - /* - * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL, - * also flush the entire Page Walk Cache. - */ - __tlbiel_pid(pid, 0, ric); + switch (ric) { + case RIC_FLUSH_PWC: - /* For PWC, only one flush is needed */ - if (ric == RIC_FLUSH_PWC) { + /* For PWC, only one flush is needed */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); ppc_after_tlbiel_barrier(); return; + case RIC_FLUSH_TLB: + __tlbiel_pid(pid, 0, RIC_FLUSH_TLB); + break; + case RIC_FLUSH_ALL: + default: + /* + * Flush the first set of the TLB, and if + * we're doing a RIC_FLUSH_ALL, also flush + * the entire Page Walk Cache. + */ + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); } if (!cpu_has_feature(CPU_FTR_ARCH_31)) { @@ -1176,7 +1184,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) } } -static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, +static void __radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, unsigned long end, int psize, bool also_pwc) { -- 2.30.2
next prev parent reply other threads:[~2021-04-22 5:44 UTC|newest] Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-22 5:43 [PATCH v5 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 1/9] selftest/mremap_test: Update the test to handle pagesize other than 4K Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 2/9] selftest/mremap_test: Avoid crash with static build Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 3/9] mm/mremap: Use pmd/pud_poplulate to update page table entries Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-05-18 20:04 ` Nathan Chancellor 2021-05-18 20:04 ` Nathan Chancellor 2021-05-19 4:46 ` Aneesh Kumar K.V 2021-05-19 4:46 ` Aneesh Kumar K.V 2021-05-19 18:02 ` Nathan Chancellor 2021-05-19 18:02 ` Nathan Chancellor 2021-05-20 2:18 ` Peter Xu 2021-05-20 2:18 ` Peter Xu 2021-05-20 8:26 ` Aneesh Kumar K.V 2021-05-20 8:26 ` Aneesh Kumar K.V 2021-05-20 12:46 ` Peter Xu 2021-05-20 12:46 ` Peter Xu 2021-05-20 13:23 ` Aneesh Kumar K.V 2021-05-20 13:23 ` Aneesh Kumar K.V 2021-05-20 13:37 ` Aneesh Kumar K.V 2021-05-20 13:37 ` Aneesh Kumar K.V 2021-05-20 14:57 ` Peter Xu 2021-05-20 14:57 ` Peter Xu 2021-05-20 19:06 ` Zi Yan 2021-05-20 19:06 ` Zi Yan 2021-05-20 20:01 ` Peter Xu 2021-05-20 20:01 ` Peter Xu 2021-05-20 20:25 ` Kalesh Singh 2021-05-20 20:25 ` Kalesh Singh 2021-04-22 5:43 ` Aneesh Kumar K.V [this message] 2021-04-22 5:43 ` [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-05-15 16:35 ` Guenter Roeck 2021-05-15 16:35 ` Guenter Roeck 2021-05-15 20:41 ` Andrew Morton 2021-05-15 20:41 ` Andrew Morton 2021-05-15 23:05 ` Guenter Roeck 2021-05-15 23:05 ` Guenter Roeck 2021-05-17 8:40 ` Aneesh Kumar K.V 2021-05-17 8:40 ` Aneesh Kumar K.V 2021-05-17 13:38 ` Guenter Roeck 2021-05-17 13:38 ` Guenter Roeck 2021-05-17 13:55 ` Aneesh Kumar K.V 2021-05-17 13:55 ` Aneesh Kumar K.V 2021-05-17 14:18 ` Guenter Roeck 2021-05-17 14:18 ` Guenter Roeck 2021-05-19 0:26 ` Michael Ellerman 2021-05-19 0:26 ` Michael Ellerman 2021-05-19 0:45 ` Segher Boessenkool 2021-05-19 0:45 ` Segher Boessenkool 2021-05-19 12:03 ` Segher Boessenkool 2021-05-19 13:37 ` Guenter Roeck 2021-05-19 14:20 ` Segher Boessenkool 2021-05-19 14:20 ` Segher Boessenkool 2021-05-19 15:28 ` Guenter Roeck 2021-05-19 15:28 ` Guenter Roeck 2021-05-20 7:37 ` Michael Ellerman 2021-05-20 12:17 ` Segher Boessenkool 2021-05-19 1:08 ` Guenter Roeck 2021-05-19 1:08 ` Guenter Roeck 2021-05-20 11:38 ` Michael Ellerman 2021-05-20 11:38 ` Michael Ellerman 2021-05-20 11:56 ` Guenter Roeck 2021-05-20 11:56 ` Guenter Roeck 2021-04-22 5:43 ` [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-05-20 15:26 ` Aneesh Kumar K.V 2021-05-20 15:26 ` Aneesh Kumar K.V 2021-05-20 16:57 ` Aneesh Kumar K.V 2021-05-20 16:57 ` Aneesh Kumar K.V 2021-05-21 2:40 ` Linus Torvalds 2021-05-21 2:40 ` Linus Torvalds 2021-05-21 3:03 ` Aneesh Kumar K.V 2021-05-21 3:03 ` Aneesh Kumar K.V 2021-05-21 3:28 ` Aneesh Kumar K.V 2021-05-21 3:28 ` Aneesh Kumar K.V 2021-05-21 6:13 ` Linus Torvalds 2021-05-21 6:13 ` Linus Torvalds 2021-05-21 12:50 ` Aneesh Kumar K.V 2021-05-21 12:50 ` Aneesh Kumar K.V 2021-05-21 13:03 ` Aneesh Kumar K.V 2021-05-21 13:03 ` Aneesh Kumar K.V 2021-05-21 16:03 ` Linus Torvalds 2021-05-21 16:03 ` Linus Torvalds 2021-05-21 16:29 ` Aneesh Kumar K.V 2021-05-21 16:29 ` Aneesh Kumar K.V 2021-05-24 14:24 ` Aneesh Kumar K.V 2021-05-24 14:24 ` Aneesh Kumar K.V 2021-05-21 15:24 ` Liam Howlett 2021-05-21 15:24 ` Liam Howlett 2021-05-21 16:02 ` Aneesh Kumar K.V 2021-05-21 16:02 ` Aneesh Kumar K.V 2021-05-21 16:05 ` Linus Torvalds 2021-05-21 16:05 ` Linus Torvalds 2021-04-22 5:43 ` [PATCH v5 8/9] mm/mremap: Allow arch runtime override Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-04-22 5:43 ` [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud Aneesh Kumar K.V 2021-04-22 5:43 ` Aneesh Kumar K.V 2021-05-11 22:19 ` Andrew Morton 2021-05-11 22:19 ` Andrew Morton
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