From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Kito Cheng <kito.cheng@sifive.com> Subject: [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend Date: Thu, 6 May 2021 00:06:16 +0800 [thread overview] Message-ID: <20210505160620.15723-16-frank.chang@sifive.com> (raw) In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++ target/riscv/translate.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 287920ee9bf..f09f8d5faf7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -720,6 +720,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r sh1add_uw 0010000 .......... 010 ..... 0111011 @r sh2add_uw 0010000 .......... 100 ..... 0111011 @r sh3add_uw 0010000 .......... 110 ..... 0111011 @r +add_uw 0000100 .......... 000 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -729,3 +730,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 + +slli_uw 00001. ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b27114a068d..9e81f6e3de4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -410,3 +410,29 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ GEN_TRANS_SHADD_UW(1) GEN_TRANS_SHADD_UW(2) GEN_TRANS_SHADD_UW(3) + +static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_add_uw); +} + +static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + + TCGv source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + if (a->shamt < 32) { + tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); + } else { + tcg_gen_shli_tl(source1, source1, a->shamt); + } + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ae9b5f7a2e2..c6e87396142 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -765,6 +765,12 @@ GEN_SHADD_UW(1) GEN_SHADD_UW(2) GEN_SHADD_UW(3) +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_add_tl(ret, arg1, arg2); +} + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng <kito.cheng@sifive.com>, Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org> Subject: [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend Date: Thu, 6 May 2021 00:06:16 +0800 [thread overview] Message-ID: <20210505160620.15723-16-frank.chang@sifive.com> (raw) In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++ target/riscv/translate.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 287920ee9bf..f09f8d5faf7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -720,6 +720,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r sh1add_uw 0010000 .......... 010 ..... 0111011 @r sh2add_uw 0010000 .......... 100 ..... 0111011 @r sh3add_uw 0010000 .......... 110 ..... 0111011 @r +add_uw 0000100 .......... 000 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -729,3 +730,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 + +slli_uw 00001. ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b27114a068d..9e81f6e3de4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -410,3 +410,29 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ GEN_TRANS_SHADD_UW(1) GEN_TRANS_SHADD_UW(2) GEN_TRANS_SHADD_UW(3) + +static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, gen_add_uw); +} + +static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + + TCGv source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + if (a->shamt < 32) { + tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); + } else { + tcg_gen_shli_tl(source1, source1, a->shamt); + } + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ae9b5f7a2e2..c6e87396142 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -765,6 +765,12 @@ GEN_SHADD_UW(1) GEN_SHADD_UW(2) GEN_SHADD_UW(3) +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_add_tl(ret, arg1, arg2); +} + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { -- 2.17.1
next prev parent reply other threads:[~2021-05-05 16:12 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang 2021-05-05 16:06 ` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-06 2:04 ` Alistair Francis 2021-05-06 2:04 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 03/17] target/riscv: rvb: count bits set frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 04/17] target/riscv: rvb: logic-with-negate frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 06/17] target/riscv: rvb: min/max instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:23 ` Alistair Francis 2021-05-10 7:23 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:24 ` Alistair Francis 2021-05-10 7:24 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 10/17] target/riscv: rvb: shift ones frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:26 ` Alistair Francis 2021-05-10 7:26 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-20 7:11 ` Alistair Francis 2021-05-20 7:11 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 12/17] target/riscv: rvb: generalized reverse frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 14/17] target/riscv: rvb: address calculation frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` frank.chang [this message] 2021-05-05 16:06 ` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang 2021-05-05 16:06 ` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-27 22:05 ` Alistair Francis 2021-05-27 22:05 ` Alistair Francis 2021-05-27 22:08 ` [PATCH v6 00/17] support subsets of bitmanip extension Alistair Francis 2021-05-27 22:08 ` Alistair Francis
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