From: Alistair Francis <alistair23@gmail.com> To: Frank Chang <frank.chang@sifive.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v6 00/17] support subsets of bitmanip extension Date: Fri, 28 May 2021 08:08:56 +1000 [thread overview] Message-ID: <CAKmqyKOFBvxxNhVhVNN+tNnS-_ed97S91UsjxriPEZi58sWHzQ@mail.gmail.com> (raw) In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> On Thu, May 6, 2021 at 2:11 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and > Zbs subset instructions. Some Zbp instructions are also implemented as > they have similar behavior with their Zba-, Zbb- and Zbs-family > instructions or for Zbb pseudo instructions (e.g. rev8, orc.b). > > Specification: > https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf > > The port is available here: > https://github.com/sifive/qemu/tree/rvb-upstream-v6 > > To test rvb implementation, specify cpu argument with 'x-b=true' or > 'x-b=true,bext_spec=v0.93'to enable B-extension support. > > Changelog: > > v6: > * rebase riscv-to-apply.next branch. > * remove all #ifdef TARGET_RISCV64 macros. > > v5: > * add bext_spec cpu option, default set to v0.93. > * rebase master branch. > > v4: > * Remove 'rd != 0' checks from immediate shift instructions. > > v3: > * Convert existing immediate shift instructions to use gen_shifti() > and gen_shiftiw() interfaces. > * Rename *u.w instructions to *.uw. > * Rename sb* instructions to b*. > * Rename pcnt* instructions to cpop*. > > v2: > * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions. > * Remove addwu, subwu and addiwu instructions as they are not longer > exist in latest draft. > * Optimize implementation with cleaner tcg ops. > > Frank Chang (6): > target/riscv: rvb: count bits set > target/riscv: add gen_shifti() and gen_shiftiw() helper functions > target/riscv: rvb: single-bit instructions > target/riscv: rvb: generalized reverse > target/riscv: rvb: generalized or-combine > target/riscv: rvb: add b-ext version cpu option > > Kito Cheng (11): > target/riscv: reformat @sh format encoding for B-extension > target/riscv: rvb: count leading/trailing zeros > target/riscv: rvb: logic-with-negate > target/riscv: rvb: pack two words into one register > target/riscv: rvb: min/max instructions > target/riscv: rvb: sign-extend instructions > target/riscv: rvb: shift ones > target/riscv: rvb: rotate (left/right) > target/riscv: rvb: address calculation > target/riscv: rvb: add/shift with prefix zero-extend > target/riscv: rvb: support and turn on B-extension from command line Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/bitmanip_helper.c | 90 +++++ > target/riscv/cpu.c | 27 ++ > target/riscv/cpu.h | 5 + > target/riscv/helper.h | 6 + > target/riscv/insn32.decode | 87 ++++- > target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++ > target/riscv/insn_trans/trans_rvi.c.inc | 54 +-- > target/riscv/meson.build | 1 + > target/riscv/translate.c | 306 +++++++++++++++++ > 9 files changed, 958 insertions(+), 56 deletions(-) > create mode 100644 target/riscv/bitmanip_helper.c > create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc > > -- > 2.17.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Frank Chang <frank.chang@sifive.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org> Subject: Re: [PATCH v6 00/17] support subsets of bitmanip extension Date: Fri, 28 May 2021 08:08:56 +1000 [thread overview] Message-ID: <CAKmqyKOFBvxxNhVhVNN+tNnS-_ed97S91UsjxriPEZi58sWHzQ@mail.gmail.com> (raw) In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> On Thu, May 6, 2021 at 2:11 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and > Zbs subset instructions. Some Zbp instructions are also implemented as > they have similar behavior with their Zba-, Zbb- and Zbs-family > instructions or for Zbb pseudo instructions (e.g. rev8, orc.b). > > Specification: > https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf > > The port is available here: > https://github.com/sifive/qemu/tree/rvb-upstream-v6 > > To test rvb implementation, specify cpu argument with 'x-b=true' or > 'x-b=true,bext_spec=v0.93'to enable B-extension support. > > Changelog: > > v6: > * rebase riscv-to-apply.next branch. > * remove all #ifdef TARGET_RISCV64 macros. > > v5: > * add bext_spec cpu option, default set to v0.93. > * rebase master branch. > > v4: > * Remove 'rd != 0' checks from immediate shift instructions. > > v3: > * Convert existing immediate shift instructions to use gen_shifti() > and gen_shiftiw() interfaces. > * Rename *u.w instructions to *.uw. > * Rename sb* instructions to b*. > * Rename pcnt* instructions to cpop*. > > v2: > * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions. > * Remove addwu, subwu and addiwu instructions as they are not longer > exist in latest draft. > * Optimize implementation with cleaner tcg ops. > > Frank Chang (6): > target/riscv: rvb: count bits set > target/riscv: add gen_shifti() and gen_shiftiw() helper functions > target/riscv: rvb: single-bit instructions > target/riscv: rvb: generalized reverse > target/riscv: rvb: generalized or-combine > target/riscv: rvb: add b-ext version cpu option > > Kito Cheng (11): > target/riscv: reformat @sh format encoding for B-extension > target/riscv: rvb: count leading/trailing zeros > target/riscv: rvb: logic-with-negate > target/riscv: rvb: pack two words into one register > target/riscv: rvb: min/max instructions > target/riscv: rvb: sign-extend instructions > target/riscv: rvb: shift ones > target/riscv: rvb: rotate (left/right) > target/riscv: rvb: address calculation > target/riscv: rvb: add/shift with prefix zero-extend > target/riscv: rvb: support and turn on B-extension from command line Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/bitmanip_helper.c | 90 +++++ > target/riscv/cpu.c | 27 ++ > target/riscv/cpu.h | 5 + > target/riscv/helper.h | 6 + > target/riscv/insn32.decode | 87 ++++- > target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++ > target/riscv/insn_trans/trans_rvi.c.inc | 54 +-- > target/riscv/meson.build | 1 + > target/riscv/translate.c | 306 +++++++++++++++++ > 9 files changed, 958 insertions(+), 56 deletions(-) > create mode 100644 target/riscv/bitmanip_helper.c > create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc > > -- > 2.17.1 > >
next prev parent reply other threads:[~2021-05-27 22:10 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang 2021-05-05 16:06 ` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-06 2:04 ` Alistair Francis 2021-05-06 2:04 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 03/17] target/riscv: rvb: count bits set frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 04/17] target/riscv: rvb: logic-with-negate frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 06/17] target/riscv: rvb: min/max instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:23 ` Alistair Francis 2021-05-10 7:23 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:24 ` Alistair Francis 2021-05-10 7:24 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 10/17] target/riscv: rvb: shift ones frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-10 7:26 ` Alistair Francis 2021-05-10 7:26 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-20 7:11 ` Alistair Francis 2021-05-20 7:11 ` Alistair Francis 2021-05-05 16:06 ` [PATCH v6 12/17] target/riscv: rvb: generalized reverse frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 14/17] target/riscv: rvb: address calculation frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-05 16:06 ` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang 2021-05-05 16:06 ` frank.chang 2021-05-27 22:05 ` Alistair Francis 2021-05-27 22:05 ` Alistair Francis 2021-05-27 22:08 ` Alistair Francis [this message] 2021-05-27 22:08 ` [PATCH v6 00/17] support subsets of bitmanip extension Alistair Francis
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