From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniele.ceraolospurio@intel.com, john.c.harrison@intel.com,
Michal.Wajdeczko@intel.com
Subject: [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool
Date: Wed, 9 Jun 2021 21:36:46 -0700 [thread overview]
Message-ID: <20210610043649.144416-11-matthew.brost@intel.com> (raw)
In-Reply-To: <20210610043649.144416-1-matthew.brost@intel.com>
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
CTB pool is now maintained internally by the GuC as part of its
"private data". No need to allocate separate buffer and pass it
to GuC as yet another ADS.
Signed-off-by: Matthew Brost <matthew.brost@intel.com> #v4
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12 ------------
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 12 +-----------
2 files changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 4fcbe4b921f9..6e26fe04ce92 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -26,8 +26,6 @@
* +---------------------------------------+
* | guc_clients_info |
* +---------------------------------------+
- * | guc_ct_pool_entry[size] |
- * +---------------------------------------+
* | padding |
* +---------------------------------------+ <== 4K aligned
* | private data |
@@ -40,7 +38,6 @@ struct __guc_ads_blob {
struct guc_policies policies;
struct guc_gt_system_info system_info;
struct guc_clients_info clients_info;
- struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
} __packed;
static u32 guc_ads_private_data_size(struct intel_guc *guc)
@@ -68,11 +65,6 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
}
-static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
-{
- memset(pool, 0, num * sizeof(*pool));
-}
-
static void guc_mapping_table_init(struct intel_gt *gt,
struct guc_gt_system_info *system_info)
{
@@ -161,11 +153,7 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Clients info */
- guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
-
blob->clients_info.clients_num = 1;
- blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
- blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 251c3836bd2c..2266444d074f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -295,19 +295,9 @@ struct guc_gt_system_info {
} __packed;
/* Clients info */
-struct guc_ct_pool_entry {
- struct guc_ct_buffer_desc desc;
- u32 reserved[7];
-} __packed;
-
-#define GUC_CT_POOL_SIZE 2
-
struct guc_clients_info {
u32 clients_num;
- u32 reserved0[13];
- u32 ct_pool_addr;
- u32 ct_pool_count;
- u32 reserved[4];
+ u32 reserved[19];
} __packed;
/* GuC Additional Data Struct */
--
2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool
Date: Wed, 9 Jun 2021 21:36:46 -0700 [thread overview]
Message-ID: <20210610043649.144416-11-matthew.brost@intel.com> (raw)
In-Reply-To: <20210610043649.144416-1-matthew.brost@intel.com>
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
CTB pool is now maintained internally by the GuC as part of its
"private data". No need to allocate separate buffer and pass it
to GuC as yet another ADS.
Signed-off-by: Matthew Brost <matthew.brost@intel.com> #v4
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12 ------------
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 12 +-----------
2 files changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 4fcbe4b921f9..6e26fe04ce92 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -26,8 +26,6 @@
* +---------------------------------------+
* | guc_clients_info |
* +---------------------------------------+
- * | guc_ct_pool_entry[size] |
- * +---------------------------------------+
* | padding |
* +---------------------------------------+ <== 4K aligned
* | private data |
@@ -40,7 +38,6 @@ struct __guc_ads_blob {
struct guc_policies policies;
struct guc_gt_system_info system_info;
struct guc_clients_info clients_info;
- struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
} __packed;
static u32 guc_ads_private_data_size(struct intel_guc *guc)
@@ -68,11 +65,6 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
}
-static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
-{
- memset(pool, 0, num * sizeof(*pool));
-}
-
static void guc_mapping_table_init(struct intel_gt *gt,
struct guc_gt_system_info *system_info)
{
@@ -161,11 +153,7 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Clients info */
- guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
-
blob->clients_info.clients_num = 1;
- blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
- blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 251c3836bd2c..2266444d074f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -295,19 +295,9 @@ struct guc_gt_system_info {
} __packed;
/* Clients info */
-struct guc_ct_pool_entry {
- struct guc_ct_buffer_desc desc;
- u32 reserved[7];
-} __packed;
-
-#define GUC_CT_POOL_SIZE 2
-
struct guc_clients_info {
u32 clients_num;
- u32 reserved0[13];
- u32 ct_pool_addr;
- u32 ct_pool_count;
- u32 reserved[4];
+ u32 reserved[19];
} __packed;
/* GuC Additional Data Struct */
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-10 4:19 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 4:36 [PATCH 00/13] Update firmware to v62.0.0 Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:16 ` Matthew Brost
2021-06-10 4:16 ` Matthew Brost
2021-06-10 4:36 ` [PATCH 01/13] drm/i915/guc: Introduce unified HXG messages Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-14 17:04 ` Daniele Ceraolo Spurio
2021-06-14 17:04 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-10 4:36 ` [PATCH 02/13] drm/i915/guc: Update MMIO based communication Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-14 18:11 ` Daniele Ceraolo Spurio
2021-06-14 18:11 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-10 4:36 ` [PATCH 03/13] drm/i915/guc: Update CTB response status definition Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:36 ` [PATCH 04/13] drm/i915/guc: Support per context scheduling policies Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:36 ` [PATCH 05/13] drm/i915/guc: Add flag for mark broken CTB Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:36 ` [PATCH 06/13] drm/i915/guc: New definition of the CTB descriptor Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-14 18:17 ` Daniele Ceraolo Spurio
2021-06-14 18:17 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-10 4:36 ` [PATCH 07/13] drm/i915/guc: New definition of the CTB registration action Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-14 18:21 ` Daniele Ceraolo Spurio
2021-06-14 18:21 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-10 4:36 ` [PATCH 08/13] drm/i915/guc: New CTB based communication Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-14 18:24 ` Daniele Ceraolo Spurio
2021-06-14 18:24 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-10 4:36 ` [PATCH 09/13] drm/i915/doc: Include GuC ABI documentation Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 13:55 ` Piotr Piórkowski
2021-06-10 13:55 ` Piotr Piórkowski
2021-06-10 4:36 ` Matthew Brost [this message]
2021-06-10 4:36 ` [Intel-gfx] [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost
2021-06-10 4:36 ` [PATCH 11/13] drm/i915/guc: Kill ads.client_info Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:36 ` [PATCH 12/13] drm/i915/guc: Unified GuC log Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 4:36 ` [PATCH 13/13] drm/i915/guc: Update firmware to v62.0.0 Matthew Brost
2021-06-10 4:36 ` [Intel-gfx] " Matthew Brost
2021-06-10 5:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update firmware to v62.0.0 (rev2) Patchwork
2021-06-10 5:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-10 5:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-10 7:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-10 13:35 ` [PATCH 00/13] Update firmware to v62.0.0 Michal Wajdeczko
2021-06-10 13:35 ` [Intel-gfx] " Michal Wajdeczko
2021-06-11 18:46 ` Matthew Brost
2021-06-11 18:46 ` [Intel-gfx] " Matthew Brost
-- strict thread matches above, loose matches on Subject: below --
2021-06-07 18:03 Matthew Brost
2021-06-07 18:03 ` [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost
2021-06-07 17:57 ` Matthew Brost
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