From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [RFC PATCH v2 10/11] clocksource: clint: Add support for ACLINT MTIMER device Date: Fri, 18 Jun 2021 18:08:50 +0530 [thread overview] Message-ID: <20210618123851.1344518-11-anup.patel@wdc.com> (raw) In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> The RISC-V ACLINT specification is a modular specification and the ACLINT MTIMER device is backward compatible with the M-mode timer functionality of the CLINT device. This patch extends the CLINT timer driver to support both CLINT device and ACLINT MTIMER device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- drivers/clocksource/timer-clint.c | 35 ++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 3b68ed53fe4a..bf89744cd12a 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -2,8 +2,16 @@ /* * Copyright (C) 2020 Western Digital Corporation or its affiliates. * - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a - * CLINT MMIO timer device. + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT + * MMIO device which is a composite device capable of injecting M-mode + * software interrupts and M-mode timer interrupts. + * + * The RISC-V ACLINT specification is modular in nature and defines + * separate devices for M-mode software interrupt (MSWI), M-mode timer + * (MTIMER) and S-mode software interrupt (SSWI). + * + * This is a common timer driver for the CLINT device and the ACLINT + * MTIMER device. */ #define pr_fmt(fmt) "clint: " fmt @@ -21,25 +29,26 @@ #include <linux/smp.h> #include <linux/timex.h> -#ifndef CONFIG_RISCV_M_MODE +#ifdef CONFIG_RISCV_M_MODE #include <asm/clint.h> + +u64 __iomem *clint_time_val; +EXPORT_SYMBOL(clint_time_val); #endif #define CLINT_IPI_OFF 0 #define CLINT_TIMER_CMP_OFF 0x4000 #define CLINT_TIMER_VAL_OFF 0xbff8 +#define ACLINT_MTIMER_CMP_OFF 0x0000 +#define ACLINT_MTIMER_VAL_OFF 0x7ff8 + /* CLINT manages IPI and Timer for RISC-V M-mode */ static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; -#ifdef CONFIG_RISCV_M_MODE -u64 __iomem *clint_time_val; -EXPORT_SYMBOL(clint_time_val); -#endif - #ifdef CONFIG_64BIT #define clint_get_cycles() readq_relaxed(clint_timer_val) #else @@ -170,8 +179,13 @@ static int __init clint_timer_init_dt(struct device_node *np) return -ENODEV; } - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; - clint_timer_val = base + CLINT_TIMER_VAL_OFF; + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) { + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF; + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF; + } else { + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; + clint_timer_val = base + CLINT_TIMER_VAL_OFF; + } clint_timer_freq = riscv_timebase; #ifdef CONFIG_RISCV_M_MODE @@ -219,3 +233,4 @@ static int __init clint_timer_init_dt(struct device_node *np) TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [RFC PATCH v2 10/11] clocksource: clint: Add support for ACLINT MTIMER device Date: Fri, 18 Jun 2021 18:08:50 +0530 [thread overview] Message-ID: <20210618123851.1344518-11-anup.patel@wdc.com> (raw) In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> The RISC-V ACLINT specification is a modular specification and the ACLINT MTIMER device is backward compatible with the M-mode timer functionality of the CLINT device. This patch extends the CLINT timer driver to support both CLINT device and ACLINT MTIMER device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- drivers/clocksource/timer-clint.c | 35 ++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 3b68ed53fe4a..bf89744cd12a 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -2,8 +2,16 @@ /* * Copyright (C) 2020 Western Digital Corporation or its affiliates. * - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a - * CLINT MMIO timer device. + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT + * MMIO device which is a composite device capable of injecting M-mode + * software interrupts and M-mode timer interrupts. + * + * The RISC-V ACLINT specification is modular in nature and defines + * separate devices for M-mode software interrupt (MSWI), M-mode timer + * (MTIMER) and S-mode software interrupt (SSWI). + * + * This is a common timer driver for the CLINT device and the ACLINT + * MTIMER device. */ #define pr_fmt(fmt) "clint: " fmt @@ -21,25 +29,26 @@ #include <linux/smp.h> #include <linux/timex.h> -#ifndef CONFIG_RISCV_M_MODE +#ifdef CONFIG_RISCV_M_MODE #include <asm/clint.h> + +u64 __iomem *clint_time_val; +EXPORT_SYMBOL(clint_time_val); #endif #define CLINT_IPI_OFF 0 #define CLINT_TIMER_CMP_OFF 0x4000 #define CLINT_TIMER_VAL_OFF 0xbff8 +#define ACLINT_MTIMER_CMP_OFF 0x0000 +#define ACLINT_MTIMER_VAL_OFF 0x7ff8 + /* CLINT manages IPI and Timer for RISC-V M-mode */ static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; -#ifdef CONFIG_RISCV_M_MODE -u64 __iomem *clint_time_val; -EXPORT_SYMBOL(clint_time_val); -#endif - #ifdef CONFIG_64BIT #define clint_get_cycles() readq_relaxed(clint_timer_val) #else @@ -170,8 +179,13 @@ static int __init clint_timer_init_dt(struct device_node *np) return -ENODEV; } - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; - clint_timer_val = base + CLINT_TIMER_VAL_OFF; + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) { + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF; + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF; + } else { + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; + clint_timer_val = base + CLINT_TIMER_VAL_OFF; + } clint_timer_freq = riscv_timebase; #ifdef CONFIG_RISCV_M_MODE @@ -219,3 +233,4 @@ static int __init clint_timer_init_dt(struct device_node *np) TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt); -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-06-18 12:40 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-18 12:38 [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 01/11] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 02/11] RISC-V: Use common print prefix in smp.c Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 13:44 ` Marc Zyngier 2021-07-26 13:44 ` Marc Zyngier 2021-07-26 15:22 ` Anup Patel 2021-07-26 15:22 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 03/11] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 04/11] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 05/11] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-12 19:22 ` Rob Herring 2021-07-12 19:22 ` Rob Herring 2021-07-13 15:27 ` Anup Patel 2021-07-13 15:27 ` Anup Patel 2021-07-27 6:32 ` Sean Anderson 2021-07-27 6:32 ` Sean Anderson 2021-06-18 12:38 ` [RFC PATCH v2 07/11] irqchip: Add ACLINT software interrupt driver Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 14:25 ` Marc Zyngier 2021-07-26 14:25 ` Marc Zyngier 2021-07-26 16:05 ` Anup Patel 2021-07-26 16:05 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 08/11] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 09/11] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` Anup Patel [this message] 2021-06-18 12:38 ` [RFC PATCH v2 10/11] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 12:45 ` [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel 2021-07-26 12:45 ` Anup Patel 2021-07-26 14:32 ` Marc Zyngier 2021-07-26 14:32 ` Marc Zyngier 2021-07-26 13:01 ` Anup Patel 2021-07-26 13:01 ` Anup Patel 2021-07-29 4:30 ` Palmer Dabbelt 2021-07-29 4:30 ` Palmer Dabbelt 2021-07-29 4:56 ` Anup Patel 2021-07-29 4:56 ` Anup Patel 2021-07-29 5:36 ` Anup Patel 2021-07-29 5:36 ` Anup Patel
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