From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com> Subject: [RFC PATCH v2 05/11] RISC-V: Use IPIs for remote TLB flush when possible Date: Fri, 18 Jun 2021 18:08:45 +0530 [thread overview] Message-ID: <20210618123851.1344518-6-anup.patel@wdc.com> (raw) In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> If IPI calls are injected using SBI IPI calls then remote TLB flush using SBI RFENCE calls is much faster because using IPIs for remote TLB flush would still endup as SBI IPI calls with extra processing on kernel side. It is now possible to have specialized hardware (such as RISC-V AIA) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 720b443c4528..009c56fa102d 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -1,39 +1,73 @@ // SPDX-License-Identifier: GPL-2.0 +/* + * TLB flush implementation. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ #include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> +static void ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (!riscv_use_ipi_for_rfence()) + sbi_remote_sfence_vma(NULL, 0, -1); + else + on_each_cpu(ipi_flush_tlb_all, NULL, 1); +} + +struct flush_range_data { + unsigned long start; + unsigned long size; +}; + +static void ipi_flush_range(void *info) +{ + struct flush_range_data *data = info; + + /* local cpu is the only cpu present in cpumask */ + if (data->size <= PAGE_SIZE) + local_flush_tlb_page(data->start); + else + local_flush_tlb_all(); } /* - * This function must not be called with cmask being null. + * This function must not be called with NULL cpumask. * Kernel may panic if cmask is NULL. */ -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, - unsigned long size) +static void flush_range(struct cpumask *cmask, unsigned long start, + unsigned long size) { + struct flush_range_data info; struct cpumask hmask; unsigned int cpuid; if (cpumask_empty(cmask)) return; + info.start = start; + info.size = size; + cpuid = get_cpu(); if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { - /* local cpu is the only cpu present in cpumask */ - if (size <= PAGE_SIZE) - local_flush_tlb_page(start); - else - local_flush_tlb_all(); + ipi_flush_range(&info); } else { - riscv_cpuid_to_hartid_mask(cmask, &hmask); - sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size); + if (!riscv_use_ipi_for_rfence()) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma(cpumask_bits(&hmask), + start, size); + } else { + on_each_cpu_mask(cmask, ipi_flush_range, &info, 1); + } } put_cpu(); @@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); + flush_range(mm_cpumask(mm), 0, -1); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); + flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); + flush_range(mm_cpumask(vma->vm_mm), start, end - start); } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com> Subject: [RFC PATCH v2 05/11] RISC-V: Use IPIs for remote TLB flush when possible Date: Fri, 18 Jun 2021 18:08:45 +0530 [thread overview] Message-ID: <20210618123851.1344518-6-anup.patel@wdc.com> (raw) In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> If IPI calls are injected using SBI IPI calls then remote TLB flush using SBI RFENCE calls is much faster because using IPIs for remote TLB flush would still endup as SBI IPI calls with extra processing on kernel side. It is now possible to have specialized hardware (such as RISC-V AIA) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 720b443c4528..009c56fa102d 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -1,39 +1,73 @@ // SPDX-License-Identifier: GPL-2.0 +/* + * TLB flush implementation. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ #include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> +static void ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (!riscv_use_ipi_for_rfence()) + sbi_remote_sfence_vma(NULL, 0, -1); + else + on_each_cpu(ipi_flush_tlb_all, NULL, 1); +} + +struct flush_range_data { + unsigned long start; + unsigned long size; +}; + +static void ipi_flush_range(void *info) +{ + struct flush_range_data *data = info; + + /* local cpu is the only cpu present in cpumask */ + if (data->size <= PAGE_SIZE) + local_flush_tlb_page(data->start); + else + local_flush_tlb_all(); } /* - * This function must not be called with cmask being null. + * This function must not be called with NULL cpumask. * Kernel may panic if cmask is NULL. */ -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, - unsigned long size) +static void flush_range(struct cpumask *cmask, unsigned long start, + unsigned long size) { + struct flush_range_data info; struct cpumask hmask; unsigned int cpuid; if (cpumask_empty(cmask)) return; + info.start = start; + info.size = size; + cpuid = get_cpu(); if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { - /* local cpu is the only cpu present in cpumask */ - if (size <= PAGE_SIZE) - local_flush_tlb_page(start); - else - local_flush_tlb_all(); + ipi_flush_range(&info); } else { - riscv_cpuid_to_hartid_mask(cmask, &hmask); - sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size); + if (!riscv_use_ipi_for_rfence()) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma(cpumask_bits(&hmask), + start, size); + } else { + on_each_cpu_mask(cmask, ipi_flush_range, &info, 1); + } } put_cpu(); @@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); + flush_range(mm_cpumask(mm), 0, -1); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); + flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); + flush_range(mm_cpumask(vma->vm_mm), start, end - start); } -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-06-18 12:39 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-18 12:38 [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 01/11] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 02/11] RISC-V: Use common print prefix in smp.c Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 13:44 ` Marc Zyngier 2021-07-26 13:44 ` Marc Zyngier 2021-07-26 15:22 ` Anup Patel 2021-07-26 15:22 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 03/11] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 04/11] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` Anup Patel [this message] 2021-06-18 12:38 ` [RFC PATCH v2 05/11] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-12 19:22 ` Rob Herring 2021-07-12 19:22 ` Rob Herring 2021-07-13 15:27 ` Anup Patel 2021-07-13 15:27 ` Anup Patel 2021-07-27 6:32 ` Sean Anderson 2021-07-27 6:32 ` Sean Anderson 2021-06-18 12:38 ` [RFC PATCH v2 07/11] irqchip: Add ACLINT software interrupt driver Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 14:25 ` Marc Zyngier 2021-07-26 14:25 ` Marc Zyngier 2021-07-26 16:05 ` Anup Patel 2021-07-26 16:05 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 08/11] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 09/11] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 10/11] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-06-18 12:38 ` [RFC PATCH v2 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel 2021-06-18 12:38 ` Anup Patel 2021-07-26 12:45 ` [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel 2021-07-26 12:45 ` Anup Patel 2021-07-26 14:32 ` Marc Zyngier 2021-07-26 14:32 ` Marc Zyngier 2021-07-26 13:01 ` Anup Patel 2021-07-26 13:01 ` Anup Patel 2021-07-29 4:30 ` Palmer Dabbelt 2021-07-29 4:30 ` Palmer Dabbelt 2021-07-29 4:56 ` Anup Patel 2021-07-29 4:56 ` Anup Patel 2021-07-29 5:36 ` Anup Patel 2021-07-29 5:36 ` Anup Patel
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