From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Sean Z <sean.z.huang@intel.com>, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Huang@freedesktop.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com> Subject: [PATCH v6 06/15] drm/i915/pxp: set KCR reg init Date: Wed, 28 Jul 2021 19:00:57 -0700 [thread overview] Message-ID: <20210729020106.18346-7-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20210729020106.18346-1-daniele.ceraolospurio@intel.com> The setting is required by hardware to allow us doing further protection operation such as sending commands to GPU or TEE. The register needs to be re-programmed on resume, so for simplicitly we bundle the programming with the component binding, which is automatically called on resume. Further HW set-up operations will be added in the same location in follow-up patches, so get ready for them by using a couple of init/fini_hw wrappers instead of calling the KCR funcs directly. v3: move programming to component binding function, rework commit msg Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +++++ 3 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 400deaea2d8a..66a98feb33ab 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -7,6 +7,24 @@ #include "gt/intel_context.h" #include "i915_drv.h" +/* KCR register definitions */ +#define KCR_INIT _MMIO(0x320f0) + +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) + +static void kcr_pxp_enable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + +static void kcr_pxp_disable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + static int create_vcs_context(struct intel_pxp *pxp) { static struct lock_class_key pxp_lock; @@ -71,5 +89,14 @@ void intel_pxp_fini(struct intel_pxp *pxp) intel_pxp_tee_component_fini(pxp); destroy_vcs_context(pxp); +} + +void intel_pxp_init_hw(struct intel_pxp *pxp) +{ + kcr_pxp_enable(pxp_to_gt(pxp)); +} +void intel_pxp_fini_hw(struct intel_pxp *pxp) +{ + kcr_pxp_disable(pxp_to_gt(pxp)); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index e87550fb9821..5427c3b28aa9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -22,6 +22,9 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp) #ifdef CONFIG_DRM_I915_PXP void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); + +void intel_pxp_init_hw(struct intel_pxp *pxp); +void intel_pxp_fini_hw(struct intel_pxp *pxp); #else static inline void intel_pxp_init(struct intel_pxp *pxp) { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 21916ec0f6ff..33130fb7113b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; + /* the component is required to fully start the PXP HW */ + intel_pxp_init_hw(pxp); + return 0; } @@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, { struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + intel_pxp_fini_hw(pxp); + pxp->pxp_component = NULL; } -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Sean Z <sean.z.huang@intel.com>, Huang@freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v6 06/15] drm/i915/pxp: set KCR reg init Date: Wed, 28 Jul 2021 19:00:57 -0700 [thread overview] Message-ID: <20210729020106.18346-7-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20210729020106.18346-1-daniele.ceraolospurio@intel.com> The setting is required by hardware to allow us doing further protection operation such as sending commands to GPU or TEE. The register needs to be re-programmed on resume, so for simplicitly we bundle the programming with the component binding, which is automatically called on resume. Further HW set-up operations will be added in the same location in follow-up patches, so get ready for them by using a couple of init/fini_hw wrappers instead of calling the KCR funcs directly. v3: move programming to component binding function, rework commit msg Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +++++ 3 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 400deaea2d8a..66a98feb33ab 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -7,6 +7,24 @@ #include "gt/intel_context.h" #include "i915_drv.h" +/* KCR register definitions */ +#define KCR_INIT _MMIO(0x320f0) + +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) + +static void kcr_pxp_enable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + +static void kcr_pxp_disable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + static int create_vcs_context(struct intel_pxp *pxp) { static struct lock_class_key pxp_lock; @@ -71,5 +89,14 @@ void intel_pxp_fini(struct intel_pxp *pxp) intel_pxp_tee_component_fini(pxp); destroy_vcs_context(pxp); +} + +void intel_pxp_init_hw(struct intel_pxp *pxp) +{ + kcr_pxp_enable(pxp_to_gt(pxp)); +} +void intel_pxp_fini_hw(struct intel_pxp *pxp) +{ + kcr_pxp_disable(pxp_to_gt(pxp)); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index e87550fb9821..5427c3b28aa9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -22,6 +22,9 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp) #ifdef CONFIG_DRM_I915_PXP void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); + +void intel_pxp_init_hw(struct intel_pxp *pxp); +void intel_pxp_fini_hw(struct intel_pxp *pxp); #else static inline void intel_pxp_init(struct intel_pxp *pxp) { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 21916ec0f6ff..33130fb7113b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; + /* the component is required to fully start the PXP HW */ + intel_pxp_init_hw(pxp); + return 0; } @@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, { struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); + intel_pxp_fini_hw(pxp); + pxp->pxp_component = NULL; } -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-29 2:02 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-29 2:00 [PATCH v6 00/15] drm/i915: Introduce Intel PXP Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:00 ` [PATCH v6 01/15] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-08-13 7:51 ` Jani Nikula 2021-07-29 2:00 ` [PATCH v6 02/15] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 20:45 ` Rodrigo Vivi 2021-07-29 20:45 ` [Intel-gfx] " Rodrigo Vivi 2021-07-29 2:00 ` [PATCH v6 03/15] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:00 ` [PATCH v6 04/15] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:00 ` [PATCH v6 05/15] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:00 ` Daniele Ceraolo Spurio [this message] 2021-07-29 2:00 ` [Intel-gfx] [PATCH v6 06/15] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio 2021-07-29 2:00 ` [PATCH v6 07/15] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:00 ` [PATCH v6 08/15] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio 2021-07-29 2:00 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:01 ` [PATCH v6 09/15] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-08-13 14:28 ` Daniel Vetter 2021-07-29 2:01 ` [PATCH v6 10/15] drm/i915/pxp: interfaces for using protected objects Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 11:10 ` Rodrigo Vivi 2021-07-29 11:10 ` [Intel-gfx] " Rodrigo Vivi 2021-07-29 15:17 ` Daniele Ceraolo Spurio 2021-07-29 15:17 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 20:40 ` Rodrigo Vivi 2021-07-29 20:40 ` [Intel-gfx] " Rodrigo Vivi 2021-08-13 14:37 ` Daniel Vetter 2021-08-13 14:42 ` Daniel Vetter 2021-08-13 15:24 ` Daniele Ceraolo Spurio 2021-08-16 15:29 ` Daniel Vetter 2021-08-13 15:18 ` Daniele Ceraolo Spurio 2021-08-16 15:15 ` Daniel Vetter 2021-08-16 15:58 ` Daniele Ceraolo Spurio 2021-08-17 9:02 ` Daniel Vetter 2021-07-29 2:01 ` [PATCH v6 11/15] drm/i915/pxp: start the arb session on demand Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:01 ` [PATCH v6 12/15] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 2:01 ` [PATCH v6 13/15] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-08-12 8:17 ` Anshuman Gupta 2021-08-23 7:50 ` Shankar, Uma 2021-07-29 2:01 ` [PATCH v6 14/15] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-08-12 8:20 ` Anshuman Gupta 2021-08-23 7:56 ` Shankar, Uma 2021-07-29 2:01 ` [PATCH v6 15/15] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio 2021-07-29 2:01 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-07-29 3:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev2) Patchwork 2021-07-29 3:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-29 3:21 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-07-29 3:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-29 9:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-08-12 12:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev4) Patchwork 2021-08-12 12:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-12 12:13 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-08-12 12:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-08-12 14:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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