From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
<linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v2 2/4] ARM: dts: at91: sama7g5: add ram controllers
Date: Mon, 23 Aug 2021 16:19:13 +0300 [thread overview]
Message-ID: <20210823131915.23857-3-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210823131915.23857-1-claudiu.beznea@microchip.com>
Add RAM and RAMC PHY controllers. These are necessary for platform
specific power management code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index cc6be6db7b80..ecabab4343b6 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -515,6 +515,18 @@ spi11: spi@400 {
};
};
+ uddrc: uddrc@e3800000 {
+ compatible = "microchip,sama7g5-uddrc";
+ reg = <0xe3800000 0x4000>;
+ status = "okay";
+ };
+
+ ddr3phy: ddr3phy@e3804000 {
+ compatible = "microchip,sama7g5-ddr3phy";
+ reg = <0xe3804000 0x1000>;
+ status = "okay";
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
<linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v2 2/4] ARM: dts: at91: sama7g5: add ram controllers
Date: Mon, 23 Aug 2021 16:19:13 +0300 [thread overview]
Message-ID: <20210823131915.23857-3-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210823131915.23857-1-claudiu.beznea@microchip.com>
Add RAM and RAMC PHY controllers. These are necessary for platform
specific power management code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index cc6be6db7b80..ecabab4343b6 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -515,6 +515,18 @@ spi11: spi@400 {
};
};
+ uddrc: uddrc@e3800000 {
+ compatible = "microchip,sama7g5-uddrc";
+ reg = <0xe3800000 0x4000>;
+ status = "okay";
+ };
+
+ ddr3phy: ddr3phy@e3804000 {
+ compatible = "microchip,sama7g5-ddr3phy";
+ reg = <0xe3804000 0x1000>;
+ status = "okay";
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.25.1
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next prev parent reply other threads:[~2021-08-23 13:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 13:19 [PATCH v2 0/4] ARM: at91: add new nodes to DT and fix for PM Claudiu Beznea
2021-08-23 13:19 ` Claudiu Beznea
2021-08-23 13:19 ` [PATCH v2 1/4] ARM: at91: pm: do not panic if ram controllers are not enabled Claudiu Beznea
2021-08-23 13:19 ` Claudiu Beznea
2021-08-23 13:19 ` Claudiu Beznea [this message]
2021-08-23 13:19 ` [PATCH v2 2/4] ARM: dts: at91: sama7g5: add ram controllers Claudiu Beznea
2021-08-23 13:19 ` [PATCH v2 3/4] ARM: dts: at91: sama7g5: add securam node Claudiu Beznea
2021-08-23 13:19 ` Claudiu Beznea
2021-08-23 13:19 ` [PATCH v2 4/4] ARM: dts: at91: sama7g5: add shdwc node Claudiu Beznea
2021-08-23 13:19 ` Claudiu Beznea
2021-09-14 14:54 ` [PATCH v2 0/4] ARM: at91: add new nodes to DT and fix for PM Nicolas Ferre
2021-09-14 14:54 ` Nicolas Ferre
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