From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Fabien Parent <fparent@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
Date: Wed, 25 Aug 2021 12:26:27 +0200 [thread overview]
Message-ID: <20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes in v3:
- Based on top of the patch that converts mmsys to schema
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 2d4ff0ce387b..96ca16927a06 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -42,6 +42,9 @@ properties:
"#clock-cells":
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
@@ -55,4 +58,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Fabien Parent <fparent@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
Date: Wed, 25 Aug 2021 12:26:27 +0200 [thread overview]
Message-ID: <20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes in v3:
- Based on top of the patch that converts mmsys to schema
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 2d4ff0ce387b..96ca16927a06 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -42,6 +42,9 @@ properties:
"#clock-cells":
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
@@ -55,4 +58,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
--
2.30.2
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Fabien Parent <fparent@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
Date: Wed, 25 Aug 2021 12:26:27 +0200 [thread overview]
Message-ID: <20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes in v3:
- Based on top of the patch that converts mmsys to schema
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 2d4ff0ce387b..96ca16927a06 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -42,6 +42,9 @@ properties:
"#clock-cells":
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
@@ -55,4 +58,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-25 10:26 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-25 10:26 [PATCH v3 0/7] Add support to the mmsys driver to be a reset controller Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 1/7] arm64: dts: mediatek: Move reset controller constants into common location Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra [this message]
2021-08-25 10:26 ` [PATCH v3 2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 16:31 ` Rob Herring
2021-08-25 16:31 ` Rob Herring
2021-08-25 16:31 ` Rob Herring
2021-08-25 10:26 ` [PATCH v3 3/7] dt-bindings: display: mediatek: add dsi reset optional property Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-25 10:26 ` [PATCH v3 4/7] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 5/7] arm64: dts: mt8183: " Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 6/7] soc: mediatek: mmsys: Add reset controller support Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:46 ` Philipp Zabel
2021-08-25 10:46 ` Philipp Zabel
2021-08-25 10:46 ` Philipp Zabel
2021-08-26 0:33 ` Chun-Kuang Hu
2021-08-26 0:33 ` Chun-Kuang Hu
2021-08-26 0:33 ` Chun-Kuang Hu
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-06 1:57 ` Nancy.Lin
2021-09-06 1:57 ` Nancy.Lin
2021-09-16 6:05 ` Hsin-Yi Wang
2021-09-16 6:05 ` Hsin-Yi Wang
2021-09-16 6:05 ` Hsin-Yi Wang
2021-08-25 10:26 ` [PATCH v3 7/7] drm/mediatek: mtk_dsi: Reset the dsi0 hardware Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
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