From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Rob Herring <robh@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/7] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
Date: Wed, 25 Aug 2021 12:26:29 +0200 [thread overview]
Message-ID: <20210825122613.v3.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v1)
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
include/dt-bindings/reset/mt8173-resets.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 17d70e2f5394..97ea3f9960b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1036,6 +1036,7 @@ mmsys: syscon@14000000 {
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1262,6 +1263,7 @@ dsi0: dsi@1401b000 {
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h
index ba8636eda5ae..6a60c7cecc4c 100644
--- a/include/dt-bindings/reset/mt8173-resets.h
+++ b/include/dt-bindings/reset/mt8173-resets.h
@@ -27,6 +27,8 @@
#define MT8173_INFRA_GCE_FAXI_RST 40
#define MT8173_INFRA_MMIOMMURST 47
+/* MMSYS resets */
+#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
/* PERICFG resets */
#define MT8173_PERI_UART0_SW_RST 0
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Rob Herring <robh@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/7] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
Date: Wed, 25 Aug 2021 12:26:29 +0200 [thread overview]
Message-ID: <20210825122613.v3.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v1)
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
include/dt-bindings/reset/mt8173-resets.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 17d70e2f5394..97ea3f9960b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1036,6 +1036,7 @@ mmsys: syscon@14000000 {
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1262,6 +1263,7 @@ dsi0: dsi@1401b000 {
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h
index ba8636eda5ae..6a60c7cecc4c 100644
--- a/include/dt-bindings/reset/mt8173-resets.h
+++ b/include/dt-bindings/reset/mt8173-resets.h
@@ -27,6 +27,8 @@
#define MT8173_INFRA_GCE_FAXI_RST 40
#define MT8173_INFRA_MMIOMMURST 47
+/* MMSYS resets */
+#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
/* PERICFG resets */
#define MT8173_PERI_UART0_SW_RST 0
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
To: linux-kernel@vger.kernel.org
Cc: matthias.bgg@gmail.com, hsinyi@chromium.org,
linux-mediatek@lists.infradead.org, jitao.shi@mediatek.com,
eizan@chromium.org, drinkcat@chromium.org,
chunkuang.hu@kernel.org, kernel@collabora.com,
Rob Herring <robh@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/7] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
Date: Wed, 25 Aug 2021 12:26:29 +0200 [thread overview]
Message-ID: <20210825122613.v3.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid> (raw)
In-Reply-To: <20210825102632.601614-1-enric.balletbo@collabora.com>
Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v1)
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
include/dt-bindings/reset/mt8173-resets.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 17d70e2f5394..97ea3f9960b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1036,6 +1036,7 @@ mmsys: syscon@14000000 {
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1262,6 +1263,7 @@ dsi0: dsi@1401b000 {
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h
index ba8636eda5ae..6a60c7cecc4c 100644
--- a/include/dt-bindings/reset/mt8173-resets.h
+++ b/include/dt-bindings/reset/mt8173-resets.h
@@ -27,6 +27,8 @@
#define MT8173_INFRA_GCE_FAXI_RST 40
#define MT8173_INFRA_MMIOMMURST 47
+/* MMSYS resets */
+#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
/* PERICFG resets */
#define MT8173_PERI_UART0_SW_RST 0
--
2.30.2
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2021-08-25 10:27 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-25 10:26 [PATCH v3 0/7] Add support to the mmsys driver to be a reset controller Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 1/7] arm64: dts: mediatek: Move reset controller constants into common location Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 16:31 ` Rob Herring
2021-08-25 16:31 ` Rob Herring
2021-08-25 16:31 ` Rob Herring
2021-08-25 10:26 ` [PATCH v3 3/7] dt-bindings: display: mediatek: add dsi reset optional property Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-26 0:31 ` Chun-Kuang Hu
2021-08-25 10:26 ` Enric Balletbo i Serra [this message]
2021-08-25 10:26 ` [PATCH v3 4/7] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 5/7] arm64: dts: mt8183: " Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` [PATCH v3 6/7] soc: mediatek: mmsys: Add reset controller support Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:46 ` Philipp Zabel
2021-08-25 10:46 ` Philipp Zabel
2021-08-25 10:46 ` Philipp Zabel
2021-08-26 0:33 ` Chun-Kuang Hu
2021-08-26 0:33 ` Chun-Kuang Hu
2021-08-26 0:33 ` Chun-Kuang Hu
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-03 14:10 ` Enric Balletbo i Serra
2021-09-06 1:57 ` Nancy.Lin
2021-09-06 1:57 ` Nancy.Lin
2021-09-16 6:05 ` Hsin-Yi Wang
2021-09-16 6:05 ` Hsin-Yi Wang
2021-09-16 6:05 ` Hsin-Yi Wang
2021-08-25 10:26 ` [PATCH v3 7/7] drm/mediatek: mtk_dsi: Reset the dsi0 hardware Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
2021-08-25 10:26 ` Enric Balletbo i Serra
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