From: Pingfan Liu <kernelfans@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: Pingfan Liu <kernelfans@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>, Sami Tolvanen <samitolvanen@google.com>, Julien Thierry <julien.thierry@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Yuichi Ito <ito-yuichi@fujitsu.com>, linux-kernel@vger.kernel.org Subject: [PATCHv2 2/5] irqchip/GICv3: expose handle_nmi() directly Date: Fri, 24 Sep 2021 21:28:34 +0800 [thread overview] Message-ID: <20210924132837.45994-3-kernelfans@gmail.com> (raw) In-Reply-To: <20210924132837.45994-1-kernelfans@gmail.com> With the previous patch, the NMI should be dispatched at irqentry level. Accordingly adjust GICv3 to utilize the hooks, so NMI handler can be dispatched. Signed-off-by: Pingfan Liu <kernelfans@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Joey Gouly <joey.gouly@arm.com> Cc: Sami Tolvanen <samitolvanen@google.com> Cc: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yuichi Ito <ito-yuichi@fujitsu.com> Cc: linux-kernel@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/include/asm/irq.h | 2 ++ drivers/irqchip/irq-gic-v3.c | 53 +++++++++++++++++++----------------- 2 files changed, 30 insertions(+), 25 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index a59b1745f458..c39627290a60 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -11,6 +11,8 @@ struct pt_regs; int set_handle_irq(void (*handle_irq)(struct pt_regs *)); #define set_handle_irq set_handle_irq int set_handle_fiq(void (*handle_fiq)(struct pt_regs *)); +int set_handle_nmi(void (*handle_nmi)(struct pt_regs *)); +int set_nmi_discriminator(bool (*discriminator)(void)); extern void (*handle_arch_irq)(struct pt_regs *regs); extern void (*handle_arch_fiq)(struct pt_regs *regs); diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fd4e9a37fea6..89dcec902a82 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -644,28 +644,12 @@ static void gic_deactivate_unhandled(u32 irqnr) } } -static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) +static bool gic_is_in_nmi(void) { - bool irqs_enabled = interrupts_enabled(regs); - int err; - - if (irqs_enabled) - nmi_enter(); - - if (static_branch_likely(&supports_deactivate_key)) - gic_write_eoir(irqnr); - /* - * Leave the PSR.I bit set to prevent other NMIs to be - * received while handling this one. - * PSR.I will be restored when we ERET to the - * interrupted context. - */ - err = handle_domain_nmi(gic_data.domain, irqnr, regs); - if (err) - gic_deactivate_unhandled(irqnr); + if (gic_supports_nmi() && unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) + return true; - if (irqs_enabled) - nmi_exit(); + return false; } static u32 do_read_iar(struct pt_regs *regs) @@ -702,21 +686,38 @@ static u32 do_read_iar(struct pt_regs *regs) return iar; } -static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +static void gic_handle_nmi(struct pt_regs *regs) { u32 irqnr; + int err; irqnr = do_read_iar(regs); /* Check for special IDs first */ if ((irqnr >= 1020 && irqnr <= 1023)) return; + if (static_branch_likely(&supports_deactivate_key)) + gic_write_eoir(irqnr); + /* + * Leave the PSR.I bit set to prevent other NMIs to be + * received while handling this one. + * PSR.I will be restored when we ERET to the + * interrupted context. + */ + err = handle_domain_nmi(gic_data.domain, irqnr, regs); + if (err) + gic_deactivate_unhandled(irqnr); +} - if (gic_supports_nmi() && - unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { - gic_handle_nmi(irqnr, regs); +static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ + u32 irqnr; + + irqnr = do_read_iar(regs); + + /* Check for special IDs first */ + if ((irqnr >= 1020 && irqnr <= 1023)) return; - } if (gic_prio_masking_enabled()) { gic_pmr_mask_irqs(); @@ -1791,6 +1792,8 @@ static int __init gic_init_bases(void __iomem *dist_base, } set_handle_irq(gic_handle_irq); + set_handle_nmi(gic_handle_nmi); + set_nmi_discriminator(gic_is_in_nmi); gic_update_rdist_properties(); -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From: Pingfan Liu <kernelfans@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: Pingfan Liu <kernelfans@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>, Sami Tolvanen <samitolvanen@google.com>, Julien Thierry <julien.thierry@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Yuichi Ito <ito-yuichi@fujitsu.com>, linux-kernel@vger.kernel.org Subject: [PATCHv2 2/5] irqchip/GICv3: expose handle_nmi() directly Date: Fri, 24 Sep 2021 21:28:34 +0800 [thread overview] Message-ID: <20210924132837.45994-3-kernelfans@gmail.com> (raw) In-Reply-To: <20210924132837.45994-1-kernelfans@gmail.com> With the previous patch, the NMI should be dispatched at irqentry level. Accordingly adjust GICv3 to utilize the hooks, so NMI handler can be dispatched. Signed-off-by: Pingfan Liu <kernelfans@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Joey Gouly <joey.gouly@arm.com> Cc: Sami Tolvanen <samitolvanen@google.com> Cc: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yuichi Ito <ito-yuichi@fujitsu.com> Cc: linux-kernel@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/include/asm/irq.h | 2 ++ drivers/irqchip/irq-gic-v3.c | 53 +++++++++++++++++++----------------- 2 files changed, 30 insertions(+), 25 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index a59b1745f458..c39627290a60 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -11,6 +11,8 @@ struct pt_regs; int set_handle_irq(void (*handle_irq)(struct pt_regs *)); #define set_handle_irq set_handle_irq int set_handle_fiq(void (*handle_fiq)(struct pt_regs *)); +int set_handle_nmi(void (*handle_nmi)(struct pt_regs *)); +int set_nmi_discriminator(bool (*discriminator)(void)); extern void (*handle_arch_irq)(struct pt_regs *regs); extern void (*handle_arch_fiq)(struct pt_regs *regs); diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fd4e9a37fea6..89dcec902a82 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -644,28 +644,12 @@ static void gic_deactivate_unhandled(u32 irqnr) } } -static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) +static bool gic_is_in_nmi(void) { - bool irqs_enabled = interrupts_enabled(regs); - int err; - - if (irqs_enabled) - nmi_enter(); - - if (static_branch_likely(&supports_deactivate_key)) - gic_write_eoir(irqnr); - /* - * Leave the PSR.I bit set to prevent other NMIs to be - * received while handling this one. - * PSR.I will be restored when we ERET to the - * interrupted context. - */ - err = handle_domain_nmi(gic_data.domain, irqnr, regs); - if (err) - gic_deactivate_unhandled(irqnr); + if (gic_supports_nmi() && unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) + return true; - if (irqs_enabled) - nmi_exit(); + return false; } static u32 do_read_iar(struct pt_regs *regs) @@ -702,21 +686,38 @@ static u32 do_read_iar(struct pt_regs *regs) return iar; } -static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +static void gic_handle_nmi(struct pt_regs *regs) { u32 irqnr; + int err; irqnr = do_read_iar(regs); /* Check for special IDs first */ if ((irqnr >= 1020 && irqnr <= 1023)) return; + if (static_branch_likely(&supports_deactivate_key)) + gic_write_eoir(irqnr); + /* + * Leave the PSR.I bit set to prevent other NMIs to be + * received while handling this one. + * PSR.I will be restored when we ERET to the + * interrupted context. + */ + err = handle_domain_nmi(gic_data.domain, irqnr, regs); + if (err) + gic_deactivate_unhandled(irqnr); +} - if (gic_supports_nmi() && - unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { - gic_handle_nmi(irqnr, regs); +static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ + u32 irqnr; + + irqnr = do_read_iar(regs); + + /* Check for special IDs first */ + if ((irqnr >= 1020 && irqnr <= 1023)) return; - } if (gic_prio_masking_enabled()) { gic_pmr_mask_irqs(); @@ -1791,6 +1792,8 @@ static int __init gic_init_bases(void __iomem *dist_base, } set_handle_irq(gic_handle_irq); + set_handle_nmi(gic_handle_nmi); + set_nmi_discriminator(gic_is_in_nmi); gic_update_rdist_properties(); -- 2.31.1
next prev parent reply other threads:[~2021-09-24 13:32 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-24 13:28 [PATCHv2 0/5] arm64/irqentry: remove duplicate housekeeping of Pingfan Liu 2021-09-24 13:28 ` Pingfan Liu 2021-09-24 13:28 ` [PATCHv2 1/5] arm64/entry-common: push the judgement of nmi ahead Pingfan Liu 2021-09-24 13:28 ` Pingfan Liu 2021-09-24 17:53 ` Mark Rutland 2021-09-24 17:53 ` Mark Rutland 2021-09-25 15:39 ` Pingfan Liu 2021-09-25 15:39 ` Pingfan Liu 2021-09-30 13:32 ` Mark Rutland 2021-09-30 13:32 ` Mark Rutland 2021-10-08 4:01 ` Pingfan Liu 2021-10-08 4:01 ` Pingfan Liu 2021-10-08 14:55 ` Pingfan Liu 2021-10-08 14:55 ` Pingfan Liu 2021-10-08 17:25 ` Mark Rutland 2021-10-08 17:25 ` Mark Rutland 2021-10-09 3:49 ` Pingfan Liu 2021-10-09 3:49 ` Pingfan Liu 2021-10-08 15:45 ` Paul E. McKenney 2021-10-08 15:45 ` Paul E. McKenney 2021-10-09 4:14 ` Pingfan Liu 2021-10-09 4:14 ` Pingfan Liu 2021-09-24 13:28 ` Pingfan Liu [this message] 2021-09-24 13:28 ` [PATCHv2 2/5] irqchip/GICv3: expose handle_nmi() directly Pingfan Liu 2021-09-24 13:28 ` [PATCHv2 3/5] kernel/irq: make irq_{enter,exit}() in handle_domain_irq() arch optional Pingfan Liu 2021-09-24 13:28 ` [PATCHv2 3/5] kernel/irq: make irq_{enter, exit}() " Pingfan Liu 2021-09-28 8:55 ` [PATCHv2 3/5] kernel/irq: make irq_{enter,exit}() " Mark Rutland 2021-09-28 8:55 ` Mark Rutland 2021-09-29 3:15 ` Pingfan Liu 2021-09-29 3:15 ` Pingfan Liu 2021-09-24 13:28 ` [PATCHv2 4/5] irqchip/GICv3: let gic_handle_irq() utilize irqentry on arm64 Pingfan Liu 2021-09-24 13:28 ` Pingfan Liu 2021-09-28 9:10 ` Mark Rutland 2021-09-28 9:10 ` Mark Rutland 2021-09-29 3:10 ` Pingfan Liu 2021-09-29 3:10 ` Pingfan Liu 2021-09-29 7:20 ` Marc Zyngier 2021-09-29 7:20 ` Marc Zyngier 2021-09-29 8:27 ` Pingfan Liu 2021-09-29 8:27 ` Pingfan Liu 2021-09-29 9:23 ` Mark Rutland 2021-09-29 9:23 ` Mark Rutland 2021-09-29 11:40 ` Pingfan Liu 2021-09-29 11:40 ` Pingfan Liu 2021-09-29 14:29 ` Pingfan Liu 2021-09-29 14:29 ` Pingfan Liu 2021-09-29 17:41 ` Mark Rutland 2021-09-29 17:41 ` Mark Rutland 2021-09-24 13:28 ` [PATCHv2 5/5] irqchip/GICv3: make reschedule-ipi light weight Pingfan Liu 2021-09-24 13:28 ` Pingfan Liu 2021-09-29 7:24 ` Marc Zyngier 2021-09-29 7:24 ` Marc Zyngier 2021-09-29 8:32 ` Pingfan Liu 2021-09-29 8:32 ` Pingfan Liu 2021-09-24 17:36 ` [PATCHv2 0/5] arm64/irqentry: remove duplicate housekeeping of Mark Rutland 2021-09-24 17:36 ` Mark Rutland 2021-09-24 22:59 ` Paul E. McKenney 2021-09-24 22:59 ` Paul E. McKenney 2021-09-27 9:23 ` Mark Rutland 2021-09-27 9:23 ` Mark Rutland 2021-09-28 0:09 ` Paul E. McKenney 2021-09-28 0:09 ` Paul E. McKenney 2021-09-28 8:32 ` Mark Rutland 2021-09-28 8:32 ` Mark Rutland 2021-09-28 8:35 ` Mark Rutland 2021-09-28 8:35 ` Mark Rutland 2021-09-28 9:52 ` Sven Schnelle 2021-09-28 9:52 ` Sven Schnelle 2021-09-28 10:26 ` Mark Rutland 2021-09-28 10:26 ` Mark Rutland 2021-09-28 13:55 ` Paul E. McKenney 2021-09-28 13:55 ` Paul E. McKenney 2021-09-25 15:12 ` Pingfan Liu 2021-09-25 15:12 ` Pingfan Liu
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