From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Subject: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Thu, 7 Oct 2021 10:47:10 -0700 [thread overview] Message-ID: <20211007174722.929993-2-richard.henderson@linaro.org> (raw) In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> Move the function to cpu_helper.c, as it is large and growing. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, fabien.portas@grenoble-inp.org Subject: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Thu, 7 Oct 2021 10:47:10 -0700 [thread overview] Message-ID: <20211007174722.929993-2-richard.henderson@linaro.org> (raw) In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> Move the function to cpu_helper.c, as it is large and growing. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { -- 2.25.1
next prev parent reply other threads:[~2021-10-07 17:52 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-07 17:47 [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` Richard Henderson [this message] 2021-10-07 17:47 ` [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson 2021-10-08 2:28 ` Alistair Francis 2021-10-08 2:28 ` Alistair Francis 2021-10-13 12:13 ` LIU Zhiwei 2021-10-13 12:13 ` LIU Zhiwei 2021-10-07 17:47 ` [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-11 23:28 ` Alistair Francis 2021-10-11 23:28 ` Alistair Francis 2021-10-13 12:18 ` LIU Zhiwei 2021-10-13 12:18 ` LIU Zhiwei 2021-10-07 17:47 ` [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-13 16:46 ` Frédéric Pétrot 2021-10-13 16:46 ` Frédéric Pétrot 2021-10-13 16:54 ` Richard Henderson 2021-10-13 16:54 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-07 17:47 ` [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-13 11:54 ` LIU Zhiwei 2021-10-13 11:54 ` LIU Zhiwei 2021-10-07 17:47 ` [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-13 11:45 ` LIU Zhiwei 2021-10-13 11:45 ` LIU Zhiwei 2021-10-07 17:47 ` [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-13 8:31 ` LIU Zhiwei 2021-10-13 8:31 ` LIU Zhiwei 2021-10-07 17:47 ` [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson 2021-10-07 17:47 ` Richard Henderson 2021-10-13 11:24 ` LIU Zhiwei 2021-10-13 11:24 ` LIU Zhiwei 2021-10-10 15:17 ` [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Frédéric Pétrot 2021-10-10 15:17 ` Frédéric Pétrot
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