From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, frederic.petrot@univ-grenoble-alpes.fr,
alistair.francis@wdc.com, fabien.portas@grenoble-inp.org
Subject: Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
Date: Wed, 13 Oct 2021 20:18:23 +0800 [thread overview]
Message-ID: <98ada787-f52c-07bd-4ab4-e92e1a6a9254@c-sky.com> (raw)
In-Reply-To: <20211007174722.929993-3-richard.henderson@linaro.org>
On 2021/10/8 上午1:47, Richard Henderson wrote:
> Move the MXL_RV* defines to enumerators.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/cpu_bits.h | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..e248c6bf6d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -364,9 +364,11 @@
> #define MISA32_MXL 0xC0000000
> #define MISA64_MXL 0xC000000000000000ULL
>
> -#define MXL_RV32 1
> -#define MXL_RV64 2
> -#define MXL_RV128 3
> +typedef enum {
> + MXL_RV32 = 1,
> + MXL_RV64 = 2,
> + MXL_RV128 = 3,
> +} RISCVMXL;
>
> /* sstatus CSR bits */
> #define SSTATUS_UIE 0x00000001
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org
Subject: Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
Date: Wed, 13 Oct 2021 20:18:23 +0800 [thread overview]
Message-ID: <98ada787-f52c-07bd-4ab4-e92e1a6a9254@c-sky.com> (raw)
In-Reply-To: <20211007174722.929993-3-richard.henderson@linaro.org>
On 2021/10/8 上午1:47, Richard Henderson wrote:
> Move the MXL_RV* defines to enumerators.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/cpu_bits.h | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..e248c6bf6d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -364,9 +364,11 @@
> #define MISA32_MXL 0xC0000000
> #define MISA64_MXL 0xC000000000000000ULL
>
> -#define MXL_RV32 1
> -#define MXL_RV64 2
> -#define MXL_RV128 3
> +typedef enum {
> + MXL_RV32 = 1,
> + MXL_RV64 = 2,
> + MXL_RV128 = 3,
> +} RISCVMXL;
>
> /* sstatus CSR bits */
> #define SSTATUS_UIE 0x00000001
next prev parent reply other threads:[~2021-10-13 12:19 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 17:47 [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-08 2:28 ` Alistair Francis
2021-10-08 2:28 ` Alistair Francis
2021-10-13 12:13 ` LIU Zhiwei
2021-10-13 12:13 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-11 23:28 ` Alistair Francis
2021-10-11 23:28 ` Alistair Francis
2021-10-13 12:18 ` LIU Zhiwei [this message]
2021-10-13 12:18 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-13 16:46 ` Frédéric Pétrot
2021-10-13 16:46 ` Frédéric Pétrot
2021-10-13 16:54 ` Richard Henderson
2021-10-13 16:54 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-13 11:54 ` LIU Zhiwei
2021-10-13 11:54 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-13 11:45 ` LIU Zhiwei
2021-10-13 11:45 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-13 8:31 ` LIU Zhiwei
2021-10-13 8:31 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-13 11:24 ` LIU Zhiwei
2021-10-13 11:24 ` LIU Zhiwei
2021-10-10 15:17 ` [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Frédéric Pétrot
2021-10-10 15:17 ` Frédéric Pétrot
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