From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, imre.deak@intel.com,
matthew.d.roper@intel.com,
Vandita Kulkarni <vandita.kulkarni@intel.com>
Subject: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
Date: Mon, 18 Oct 2021 12:22:04 +0530 [thread overview]
Message-ID: <20211018065207.30587-2-vandita.kulkarni@intel.com> (raw)
In-Reply-To: <20211018065207.30587-1-vandita.kulkarni@intel.com>
Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9ee62707ec72..8c166f92f8bd 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
if (DISPLAY_VER(i915) == 13) {
for_each_dsi_port(port, intel_dsi->ports)
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
- TGL_DSI_CHKN_LSHS_GB, 0x4);
+ TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..e4b1f80ca5eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11728,7 +11728,8 @@ enum skl_power_gate {
#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \
_TGL_DSI_CHKN_REG_0, \
_TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
--
2.32.0
next prev parent reply other threads:[~2021-10-18 6:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 6:52 [Intel-gfx] [PATCH 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
2021-10-18 6:52 ` Vandita Kulkarni [this message]
2021-10-19 10:05 ` [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Jani Nikula
2021-10-19 10:15 ` Ville Syrjälä
2021-10-19 10:28 ` Jani Nikula
2021-10-19 10:41 ` Ville Syrjälä
2021-10-19 10:50 ` Ville Syrjälä
2021-10-19 11:27 ` Kulkarni, Vandita
2021-10-18 6:52 ` [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
2021-10-19 10:13 ` Jani Nikula
2021-10-19 11:40 ` Kulkarni, Vandita
2021-10-19 11:45 ` Jani Nikula
2021-10-18 6:52 ` [Intel-gfx] [PATCH 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
2021-10-19 10:24 ` Jani Nikula
2021-10-19 12:08 ` Imre Deak
2021-10-18 6:52 ` [Intel-gfx] [PATCH 4/4] drm/i915/dsi: Ungate clock before enabling the phy Vandita Kulkarni
2021-10-19 10:18 ` Jani Nikula
2021-10-19 11:32 ` Kulkarni, Vandita
2021-10-19 11:43 ` Kulkarni, Vandita
2021-10-19 11:46 ` Jani Nikula
2021-10-19 11:48 ` Kulkarni, Vandita
2021-10-18 7:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP Patchwork
2021-10-18 7:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-18 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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