From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: [PATCH 5/9] drm/i915/userptr: add paranoid flush-on-acquire
Date: Mon, 18 Oct 2021 18:45:04 +0100 [thread overview]
Message-ID: <20211018174508.2137279-5-matthew.auld@intel.com> (raw)
In-Reply-To: <20211018174508.2137279-1-matthew.auld@intel.com>
Even though userptr objects are always coherent with the GPU, with no
way for userspace to change this with the set_caching ioctl, even on
non-LLC platforms, there is still the 'Bypass LCC' mocs setting, which
might permit reading the contents of main memory directly.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 887aca9e8dd2..3173c9f9a040 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -165,8 +165,11 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
goto err;
}
- sg_page_sizes = i915_sg_dma_sizes(st->sgl);
+ WARN_ON_ONCE(!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE));
+ if (i915_gem_object_can_bypass_llc(obj))
+ obj->cache_dirty = true;
+ sg_page_sizes = i915_sg_dma_sizes(st->sgl);
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
--
2.26.3
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: [Intel-gfx] [PATCH 5/9] drm/i915/userptr: add paranoid flush-on-acquire
Date: Mon, 18 Oct 2021 18:45:04 +0100 [thread overview]
Message-ID: <20211018174508.2137279-5-matthew.auld@intel.com> (raw)
In-Reply-To: <20211018174508.2137279-1-matthew.auld@intel.com>
Even though userptr objects are always coherent with the GPU, with no
way for userspace to change this with the set_caching ioctl, even on
non-LLC platforms, there is still the 'Bypass LCC' mocs setting, which
might permit reading the contents of main memory directly.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 887aca9e8dd2..3173c9f9a040 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -165,8 +165,11 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
goto err;
}
- sg_page_sizes = i915_sg_dma_sizes(st->sgl);
+ WARN_ON_ONCE(!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE));
+ if (i915_gem_object_can_bypass_llc(obj))
+ obj->cache_dirty = true;
+ sg_page_sizes = i915_sg_dma_sizes(st->sgl);
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
--
2.26.3
next prev parent reply other threads:[~2021-10-18 17:49 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 17:45 [PATCH 1/9] drm/i915: mark dmabuf objects as ALLOC_USER Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-18 17:45 ` [PATCH 2/9] drm/i915: mark userptr " Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 14:36 ` Thomas Hellström
2021-10-20 14:36 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [PATCH 3/9] drm/i915: extract bypass-llc check into helper Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 14:38 ` Thomas Hellström
2021-10-20 14:38 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [Intel-gfx] [PATCH 4/9] drm/i915/dmabuf: add paranoid flush-on-acquire Matthew Auld
2021-10-18 17:45 ` Matthew Auld
2021-10-20 14:42 ` Thomas Hellström
2021-10-20 14:42 ` [Intel-gfx] " Thomas Hellström
2021-10-22 10:50 ` kernel test robot
2021-10-26 13:44 ` Guenter Roeck
2021-10-26 13:44 ` [Intel-gfx] " Guenter Roeck
2021-10-18 17:45 ` Matthew Auld [this message]
2021-10-18 17:45 ` [Intel-gfx] [PATCH 5/9] drm/i915/userptr: " Matthew Auld
2021-10-20 14:52 ` Thomas Hellström
2021-10-20 14:52 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [PATCH 6/9] drm/i915/shmem: ensure flush during swap-in on non-LLC Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 14:53 ` Thomas Hellström
2021-10-20 14:53 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [PATCH 7/9] drm/i915: expand on the kernel-doc for cache_dirty Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 14:58 ` Thomas Hellström
2021-10-20 14:58 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [PATCH 8/9] drm/i915: mark up internal objects with start_cpu_write Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 15:11 ` Thomas Hellström
2021-10-20 15:11 ` [Intel-gfx] " Thomas Hellström
2021-10-18 17:45 ` [PATCH 9/9] drm/i915/selftests: mark up hugepages object " Matthew Auld
2021-10-18 17:45 ` [Intel-gfx] " Matthew Auld
2021-10-20 15:12 ` Thomas Hellström
2021-10-20 15:12 ` [Intel-gfx] " Thomas Hellström
2021-10-18 19:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915: mark dmabuf objects as ALLOC_USER Patchwork
2021-10-18 19:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-18 19:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-19 2:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-20 14:34 ` [PATCH 1/9] " Thomas Hellström
2021-10-20 14:34 ` [Intel-gfx] " Thomas Hellström
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