Re: [PATCH v8 01/40] x86/compressed/64: detect/setup SEV/SME features earlier in boot

From: Michael Roth <michael.roth@amd.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Venu Busireddy <venu.busireddy@oracle.com>,
	Borislav Petkov <bp@alien8.de>,
	Brijesh Singh <brijesh.singh@amd.com>, <x86@kernel.org>,
	<linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>,
	<linux-efi@vger.kernel.org>,
	<platform-driver-x86@vger.kernel.org>,
	<linux-coco@lists.linux.dev>, <linux-mm@kvack.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Joerg Roedel <jroedel@suse.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Jim Mattson <jmattson@google.com>,
	Andy Lutomirski <luto@kernel.org>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>,
	Peter Zijlstra <peterz@infradead.org>,
	"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
	David Rientjes <rientjes@google.com>,
	Dov Murik <dovmurik@linux.ibm.com>,
	"Tobin Feldman-Fitzthum" <tobin@ibm.com>,
	Vlastimil Babka <vbabka@suse.cz>,
	"Kirill A . Shutemov" <kirill@shutemov.name>,
	Andi Kleen <ak@linux.intel.com>,
	"Dr . David Alan Gilbert" <dgilbert@redhat.com>,
	<tony.luck@intel.com>, <marcorr@google.com>,
	<sathyanarayanan.kuppuswamy@linux.intel.com>
Subject: Re: [PATCH v8 01/40] x86/compressed/64: detect/setup SEV/SME features earlier in boot
Date: Wed, 15 Dec 2021 11:49:34 -0600	[thread overview]
Message-ID: <20211215174934.tgn3c7c4s3toelbq@amd.com> (raw)
In-Reply-To: <b18655e3-3922-2b5d-0c35-1dcfef568e4d@amd.com>

On Wed, Dec 15, 2021 at 08:43:23AM -0600, Tom Lendacky wrote:
> On 12/14/21 6:14 PM, Venu Busireddy wrote:
> > On 2021-12-14 20:10:16 +0100, Borislav Petkov wrote:
> > > On Tue, Dec 14, 2021 at 11:46:14AM -0600, Venu Busireddy wrote:
> > > > What I am suggesting should not have anything to do with the boot stage
> > > > of the kernel.
> > > 
> > > I know exactly what you're suggesting.
> > > 
> > > > For example, both these functions call native_cpuid(), which is declared
> > > > as an inline function. I am merely suggesting to do something similar
> > > > to avoid the code duplication.
> > > 
> > > Try it yourself. If you can come up with something halfway readable and
> > > it builds, I'm willing to take a look.
> > 
> > Patch (to be applied on top of sev-snp-v8 branch of
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FAMDESE%2Flinux.git&amp;data=04%7C01%7Cthomas.lendacky%40amd.com%7Cbff83ee03b1147c39ea808d9bf5fe9d8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637751240978266883%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=D8t%2FwXY%2FYIl8aJXN%2BU7%2Flubln8AbhtdgB0f4DCNWp4w%3D&amp;reserved=0) is attached at the end.
> > 
> > Here are a few things I did.
> > 
> > 1. Moved all the common code that existed at the begining of
> >     sme_enable() and sev_enable() to an inline function named
> >     get_pagetable_bit_pos().
> > 2. sme_enable() was using AMD_SME_BIT and AMD_SEV_BIT, whereas
> >     sev_enable() was dealing with raw bits. Moved those definitions to
> >     sev.h, and changed sev_enable() to use those definitions.
> > 3. Make consistent use of BIT_ULL.
> > 
> > Venu
> > 
> > 
> > diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
> > index c2bf99522e5e..b44d6b37796e 100644
> > --- a/arch/x86/boot/compressed/sev.c
> > +++ b/arch/x86/boot/compressed/sev.c
> > @@ -291,6 +291,7 @@ static void enforce_vmpl0(void)
> >   void sev_enable(struct boot_params *bp)
> >   {
> >   	unsigned int eax, ebx, ecx, edx;
> > +	unsigned long pt_bit_pos;	/* Pagetable bit position */
> >   	bool snp;
> >   	/*
> > @@ -299,26 +300,8 @@ void sev_enable(struct boot_params *bp)
> >   	 */
> >   	snp = snp_init(bp);
> > -	/* Check for the SME/SEV support leaf */
> > -	eax = 0x80000000;
> > -	ecx = 0;
> > -	native_cpuid(&eax, &ebx, &ecx, &edx);
> > -	if (eax < 0x8000001f)
> > -		return;
> > -
> > -	/*
> > -	 * Check for the SME/SEV feature:
> > -	 *   CPUID Fn8000_001F[EAX]
> > -	 *   - Bit 0 - Secure Memory Encryption support
> > -	 *   - Bit 1 - Secure Encrypted Virtualization support
> > -	 *   CPUID Fn8000_001F[EBX]
> > -	 *   - Bits 5:0 - Pagetable bit position used to indicate encryption
> > -	 */
> > -	eax = 0x8000001f;
> > -	ecx = 0;
> > -	native_cpuid(&eax, &ebx, &ecx, &edx);
> > -	/* Check whether SEV is supported */
> > -	if (!(eax & BIT(1))) {
> > +	/* Get the pagetable bit position if SEV is supported */
> > +	if ((get_pagetable_bit_pos(&pt_bit_pos, AMD_SEV_BIT)) < 0) {
> >   		if (snp)
> >   			error("SEV-SNP support indicated by CC blob, but not CPUID.");
> >   		return;
> > @@ -350,7 +333,7 @@ void sev_enable(struct boot_params *bp)
> >   	if (snp && !(sev_status & MSR_AMD64_SEV_SNP_ENABLED))
> >   		error("SEV-SNP supported indicated by CC blob, but not SEV status MSR.");
> > -	sme_me_mask = BIT_ULL(ebx & 0x3f);
> > +	sme_me_mask = BIT_ULL(pt_bit_pos);
> >   }
> >   /* Search for Confidential Computing blob in the EFI config table. */
> > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> > index 2c5f12ae7d04..41b096f28d02 100644
> > --- a/arch/x86/include/asm/processor.h
> > +++ b/arch/x86/include/asm/processor.h
> > @@ -224,6 +224,43 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
> >   	    : "memory");
> >   }
> > +/*
> > + * Returns the pagetable bit position in pt_bit_pos,
> > + * iff the specified features are supported.
> > + */
> > +static inline int get_pagetable_bit_pos(unsigned long *pt_bit_pos,
> > +					unsigned long features)
> 
> I'm not a fan of this name. You are specifically returning the encryption
> bit position but using a very generic name of get_pagetable_bit_pos() in a
> very common header file. Maybe something more like get_me_bit() and move the
> function to an existing SEV header file.
> 
> Also, this can probably just return an unsigned int that will be either 0 or
> the bit position, right?  Then the check above can be for a zero value,
> e.g.:
> 
> 	me_bit = get_me_bit();
> 	if (!me_bit) {
> 
> 	...
> 
> 	sme_me_mask = BIT_ULL(me_bit);
> 
> That should work below, too, but you'll need to verify that.

I think in the greater context of consolidating all the SME/SEV setup
and re-using code, this helper stands a high chance of eventually becoming
something more along the lines of sme_sev_parse_cpuid(), since otherwise
we'd end up re-introducing multiple helpers to parse the same 0x8000001F
fields if we ever need to process any of the other fields advertised in
there. Given that, it makes sense to reserve the return value as an
indication that either SEV or SME are enabled, and then have a
pass-by-pointer parameters list to collect the individual feature
bits/encryption mask for cases where SEV/SME are enabled, which are only
treated as valid if sme_sev_parse_cpuid() returns 0.

So Venu's original approach of passing the encryption mask by pointer
seems a little closer toward that end, but I also agree Tom's approach
is cleaner for the current code base, so I'm fine either way, just
figured I'd mention this.

I think needing to pass in the SME/SEV CPUID bits to tell the helper when
to parse encryption bit and when not to is a little bit awkward though.
If there's some agreement that this will ultimately serve the purpose of
handling all (or most) of SME/SEV-related CPUID parsing, then the caller
shouldn't really need to be aware of any individual bit positions.
Maybe a bool could handle that instead, e.g.:

  int get_me_bit(bool sev_only, ...)

  or

  int sme_sev_parse_cpuid(bool sev_only, ...)

where for boot/compressed sev_only=true, for kernel proper sev_only=false.