From: Swapnil Jakhade <sjakhade@cadence.com> To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>, <p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <a-govindraju@ti.com> Subject: [PATCH v4 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Date: Thu, 23 Dec 2021 07:01:29 +0100 [thread overview] Message-ID: <20211223060137.9252-8-sjakhade@cadence.com> (raw) In-Reply-To: <20211223060137.9252-1-sjakhade@cadence.com> Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> --- drivers/phy/cadence/phy-cadence-sierra.c | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 9f2b8aefee9c..0bfd13843f2e 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -148,6 +148,7 @@ /* PHY PCS common registers */ #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ (0xc000 << (block_offset)) +#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 #define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 @@ -256,6 +257,8 @@ struct cdns_sierra_data { u32 id_value; u8 block_offset_shift; u8 reg_offset_shift; + struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] [NUM_SSC_MODE]; struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] @@ -364,6 +367,7 @@ static int cdns_sierra_phy_init(struct phy *gphy) enum cdns_sierra_phy_type phy_type = ins->phy_type; enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; const struct cdns_reg_pairs *reg_pairs; + struct cdns_sierra_vals *pcs_cmn_vals; struct regmap *regmap; u32 num_regs; int i, j; @@ -375,6 +379,16 @@ static int cdns_sierra_phy_init(struct phy *gphy) clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); + /* PHY PCS common registers configurations */ + pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; + if (pcs_cmn_vals) { + reg_pairs = pcs_cmn_vals->reg_pairs; + num_regs = pcs_cmn_vals->num_regs; + regmap = phy->regmap_phy_pcs_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); + } + /* PMA common registers configurations */ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; if (pma_cmn_vals) { @@ -1022,6 +1036,16 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) return 0; } +/* PCIE PHY PCS common configuration */ +static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { + {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} +}; + +static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { + .reg_pairs = pcie_phy_pcs_cmn_regs, + .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), +}; + /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, @@ -1173,6 +1197,13 @@ static const struct cdns_sierra_data cdns_map_sierra = { .id_value = SIERRA_MACRO_ID, .block_offset_shift = 0x2, .reg_offset_shift = 0x2, + .pcs_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_NONE] = { + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, + }, + }, + }, .pma_cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { @@ -1203,6 +1234,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { .id_value = SIERRA_MACRO_ID, .block_offset_shift = 0x0, .reg_offset_shift = 0x1, + .pcs_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_NONE] = { + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, + }, + }, + }, .pma_cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { -- 2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Swapnil Jakhade <sjakhade@cadence.com> To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>, <p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <a-govindraju@ti.com> Subject: [PATCH v4 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Date: Thu, 23 Dec 2021 07:01:29 +0100 [thread overview] Message-ID: <20211223060137.9252-8-sjakhade@cadence.com> (raw) In-Reply-To: <20211223060137.9252-1-sjakhade@cadence.com> Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> --- drivers/phy/cadence/phy-cadence-sierra.c | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 9f2b8aefee9c..0bfd13843f2e 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -148,6 +148,7 @@ /* PHY PCS common registers */ #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ (0xc000 << (block_offset)) +#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 #define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_MACRO_ID 0x00007364 @@ -256,6 +257,8 @@ struct cdns_sierra_data { u32 id_value; u8 block_offset_shift; u8 reg_offset_shift; + struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] [NUM_SSC_MODE]; struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] @@ -364,6 +367,7 @@ static int cdns_sierra_phy_init(struct phy *gphy) enum cdns_sierra_phy_type phy_type = ins->phy_type; enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; const struct cdns_reg_pairs *reg_pairs; + struct cdns_sierra_vals *pcs_cmn_vals; struct regmap *regmap; u32 num_regs; int i, j; @@ -375,6 +379,16 @@ static int cdns_sierra_phy_init(struct phy *gphy) clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); + /* PHY PCS common registers configurations */ + pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; + if (pcs_cmn_vals) { + reg_pairs = pcs_cmn_vals->reg_pairs; + num_regs = pcs_cmn_vals->num_regs; + regmap = phy->regmap_phy_pcs_common_cdb; + for (i = 0; i < num_regs; i++) + regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); + } + /* PMA common registers configurations */ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; if (pma_cmn_vals) { @@ -1022,6 +1036,16 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) return 0; } +/* PCIE PHY PCS common configuration */ +static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { + {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} +}; + +static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { + .reg_pairs = pcie_phy_pcs_cmn_regs, + .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), +}; + /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, @@ -1173,6 +1197,13 @@ static const struct cdns_sierra_data cdns_map_sierra = { .id_value = SIERRA_MACRO_ID, .block_offset_shift = 0x2, .reg_offset_shift = 0x2, + .pcs_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_NONE] = { + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, + }, + }, + }, .pma_cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { @@ -1203,6 +1234,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { .id_value = SIERRA_MACRO_ID, .block_offset_shift = 0x0, .reg_offset_shift = 0x1, + .pcs_cmn_vals = { + [TYPE_PCIE] = { + [TYPE_NONE] = { + [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, + }, + }, + }, .pma_cmn_vals = { [TYPE_PCIE] = { [TYPE_NONE] = { -- 2.26.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2021-12-23 6:14 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-23 6:01 [PATCH v4 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade [this message] 2021-12-23 6:01 ` [PATCH v4 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-23 6:01 ` [PATCH v4 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade 2021-12-23 6:01 ` Swapnil Jakhade 2021-12-27 11:07 ` [PATCH v4 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Vinod Koul 2021-12-27 11:07 ` Vinod Koul
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211223060137.9252-8-sjakhade@cadence.com \ --to=sjakhade@cadence.com \ --cc=a-govindraju@ti.com \ --cc=devicetree@vger.kernel.org \ --cc=kishon@ti.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-phy@lists.infradead.org \ --cc=mparab@cadence.com \ --cc=p.zabel@pengutronix.de \ --cc=robh+dt@kernel.org \ --cc=vkoul@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.