From: Alim Akhtar <alim.akhtar@samsung.com>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: soc@kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, olof@lixom.net, arnd@arndb.de,
linus.walleij@linaro.org, catalin.marinas@arm.com,
robh+dt@kernel.org, krzysztof.kozlowski@canonical.com,
s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org,
pankaj.dubey@samsung.com, Alim Akhtar <alim.akhtar@samsung.com>,
linux-fsd@tesla.com, Sathyakam M <sathya@samsung.com>
Subject: [PATCH v2 10/16] clk: samsung: fsd: Add cam_csi block clock information
Date: Tue, 18 Jan 2022 20:18:45 +0530 [thread overview]
Message-ID: <20220118144851.69537-11-alim.akhtar@samsung.com> (raw)
In-Reply-To: <20220118144851.69537-1-alim.akhtar@samsung.com>
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.
Cc: linux-fsd@tesla.com
Signed-off-by: Sathyakam M <sathya@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 72a2b38524a1..afac8760ebe1 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1543,6 +1543,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
+/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
+#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
+#define PLL_CON0_PLL_CAM_CSI 0x100
+#define DIV_CAM_CSI0_ACLK 0x1800
+#define DIV_CAM_CSI1_ACLK 0x1804
+#define DIV_CAM_CSI2_ACLK 0x1808
+#define DIV_CAM_CSI_BUSD 0x180c
+#define DIV_CAM_CSI_BUSP 0x1810
+#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
+#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
+#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
+#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
+
+static const unsigned long cam_csi_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CAM_CSI,
+ PLL_CON0_PLL_CAM_CSI,
+ DIV_CAM_CSI0_ACLK,
+ DIV_CAM_CSI1_ACLK,
+ DIV_CAM_CSI2_ACLK,
+ DIV_CAM_CSI_BUSD,
+ DIV_CAM_CSI_BUSP,
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 12, 0),
+};
+
+static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
+ PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
+};
+
+PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
+
+static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
+ MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
+};
+
+static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
+ DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
+ DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
+};
+
+static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
+ GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
+ "dout_cam_csi_busd",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
+ "dout_cam_csi_busp",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
+ .pll_clks = cam_csi_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
+ .mux_clks = cam_csi_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
+ .div_clks = cam_csi_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
+ .gate_clks = cam_csi_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
+ .nr_clk_ids = CAM_CSI_NR_CLK,
+ .clk_regs = cam_csi_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1574,6 +1778,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-cam_csi",
+ .data = &cam_csi_cmu_info,
}, {
},
};
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Alim Akhtar <alim.akhtar@samsung.com>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: soc@kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, olof@lixom.net, arnd@arndb.de,
linus.walleij@linaro.org, catalin.marinas@arm.com,
robh+dt@kernel.org, krzysztof.kozlowski@canonical.com,
s.nawrocki@samsung.com, linux-samsung-soc@vger.kernel.org,
pankaj.dubey@samsung.com, Alim Akhtar <alim.akhtar@samsung.com>,
linux-fsd@tesla.com, Sathyakam M <sathya@samsung.com>
Subject: [PATCH v2 10/16] clk: samsung: fsd: Add cam_csi block clock information
Date: Tue, 18 Jan 2022 20:18:45 +0530 [thread overview]
Message-ID: <20220118144851.69537-11-alim.akhtar@samsung.com> (raw)
In-Reply-To: <20220118144851.69537-1-alim.akhtar@samsung.com>
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.
Cc: linux-fsd@tesla.com
Signed-off-by: Sathyakam M <sathya@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 72a2b38524a1..afac8760ebe1 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1543,6 +1543,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
+/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
+#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
+#define PLL_CON0_PLL_CAM_CSI 0x100
+#define DIV_CAM_CSI0_ACLK 0x1800
+#define DIV_CAM_CSI1_ACLK 0x1804
+#define DIV_CAM_CSI2_ACLK 0x1808
+#define DIV_CAM_CSI_BUSD 0x180c
+#define DIV_CAM_CSI_BUSP 0x1810
+#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
+#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
+#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
+#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
+
+static const unsigned long cam_csi_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CAM_CSI,
+ PLL_CON0_PLL_CAM_CSI,
+ DIV_CAM_CSI0_ACLK,
+ DIV_CAM_CSI1_ACLK,
+ DIV_CAM_CSI2_ACLK,
+ DIV_CAM_CSI_BUSD,
+ DIV_CAM_CSI_BUSP,
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 12, 0),
+};
+
+static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
+ PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
+};
+
+PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
+
+static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
+ MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
+};
+
+static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
+ DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
+ DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
+};
+
+static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
+ GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
+ "dout_cam_csi_busd",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
+ "dout_cam_csi_busp",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
+ .pll_clks = cam_csi_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
+ .mux_clks = cam_csi_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
+ .div_clks = cam_csi_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
+ .gate_clks = cam_csi_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
+ .nr_clk_ids = CAM_CSI_NR_CLK,
+ .clk_regs = cam_csi_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1574,6 +1778,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-cam_csi",
+ .data = &cam_csi_cmu_info,
}, {
},
};
--
2.25.1
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next prev parent reply other threads:[~2022-01-18 15:02 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220118150008epcas5p40d1c79616bb17797e79e1769f5e2c19c@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 00/16] Add support for Tesla Full Self-Driving (FSD) SoC Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
[not found] ` <CGME20220118150014epcas5p2ac07759961be616d01de76026e58d4f5@epcas5p2.samsung.com>
2022-01-18 14:48 ` [PATCH v2 01/16] dt-bindings: add vendor prefix for Tesla Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
[not found] ` <CGME20220118150018epcas5p32642af7af63869d08a861d00d97e3b68@epcas5p3.samsung.com>
2022-01-18 14:48 ` [PATCH v2 02/16] dt-bindings: clock: Add bindings definitions for FSD CMU blocks Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 16:18 ` Krzysztof Kozlowski
2022-01-18 16:18 ` Krzysztof Kozlowski
2022-01-19 20:11 ` Stephen Boyd
2022-01-19 20:11 ` Stephen Boyd
[not found] ` <CGME20220118150022epcas5p21912423606220552a78c7e22e4133a05@epcas5p2.samsung.com>
2022-01-18 14:48 ` [PATCH v2 03/16] dt-bindings: clock: Document FSD CMU bindings Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:24 ` Krzysztof Kozlowski
2022-01-18 18:24 ` Krzysztof Kozlowski
2022-01-19 20:12 ` Stephen Boyd
2022-01-19 20:12 ` Stephen Boyd
[not found] ` <CGME20220118150028epcas5p282c05b78f28a9b11d46da94e78330f0c@epcas5p2.samsung.com>
2022-01-18 14:48 ` [PATCH v2 04/16] clk: samsung: fsd: Add initial clock support Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:31 ` Krzysztof Kozlowski
2022-01-18 18:31 ` Krzysztof Kozlowski
2022-01-19 14:20 ` Alim Akhtar
2022-01-19 14:20 ` Alim Akhtar
2022-01-19 20:15 ` Stephen Boyd
2022-01-19 20:15 ` Stephen Boyd
2022-01-20 13:53 ` Alim Akhtar
2022-01-20 13:53 ` Alim Akhtar
2022-01-20 17:46 ` Stephen Boyd
2022-01-20 17:46 ` Stephen Boyd
[not found] ` <CGME20220118150033epcas5p15b88d4f0c695fc515f20d8dffe15202e@epcas5p1.samsung.com>
2022-01-18 14:48 ` [PATCH v2 05/16] clk: samsung: fsd: Add cmu_peric block clock information Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:34 ` Krzysztof Kozlowski
2022-01-18 18:34 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150037epcas5p1624361eb48fa14cdf9ed88de6f890db4@epcas5p1.samsung.com>
2022-01-18 14:48 ` [PATCH v2 06/16] clk: samsung: fsd: Add cmu_fsys0 " Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:34 ` Krzysztof Kozlowski
2022-01-18 18:34 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150041epcas5p2634381919d0e9f60867d6087162fa134@epcas5p2.samsung.com>
2022-01-18 14:48 ` [PATCH v2 07/16] clk: samsung: fsd: Add cmu_fsys1 " Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:34 ` Krzysztof Kozlowski
2022-01-18 18:34 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150045epcas5p4e54922758fb7922b1fd8de0995d2127e@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 08/16] clk: samsung: fsd: Add cmu_imem block " Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:36 ` Krzysztof Kozlowski
2022-01-18 18:36 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150048epcas5p3449136cf0dbc2186d91c4472e9df68e0@epcas5p3.samsung.com>
2022-01-18 14:48 ` [PATCH v2 09/16] clk: samsung: fsd: Add cmu_mfc " Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:36 ` Krzysztof Kozlowski
2022-01-18 18:36 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150052epcas5p12efa399d1a59fc2fb0595eef128ffdf9@epcas5p1.samsung.com>
2022-01-18 14:48 ` Alim Akhtar [this message]
2022-01-18 14:48 ` [PATCH v2 10/16] clk: samsung: fsd: Add cam_csi " Alim Akhtar
2022-01-18 18:36 ` Krzysztof Kozlowski
2022-01-18 18:36 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150056epcas5p4825077a17b8c37b0e7cea60c4dced3c8@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 11/16] dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:38 ` Krzysztof Kozlowski
2022-01-18 18:38 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150100epcas5p3b7cf28e13fd177336dc9b06875d94f43@epcas5p3.samsung.com>
2022-01-18 14:48 ` [PATCH v2 12/16] pinctrl: samsung: add FSD SoC specific data Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:48 ` Krzysztof Kozlowski
2022-01-18 18:48 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150104epcas5p4ac6fdc739d21c7d7eb2e53e469466487@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 13/16] dt-bindings: arm: add Tesla FSD ARM SoC Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:40 ` Krzysztof Kozlowski
2022-01-18 18:40 ` Krzysztof Kozlowski
2022-01-18 18:41 ` Krzysztof Kozlowski
2022-01-18 18:41 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150108epcas5p2d9cd4db7cb368c2bfbd7d058eba4107c@epcas5p2.samsung.com>
2022-01-18 14:48 ` [PATCH v2 14/16] arm64: dts: fsd: Add initial device tree support Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:45 ` Krzysztof Kozlowski
2022-01-18 18:45 ` Krzysztof Kozlowski
2022-01-19 15:07 ` Alim Akhtar
2022-01-19 15:07 ` Alim Akhtar
2022-01-19 15:11 ` 'Krzysztof Kozlowski'
2022-01-19 15:11 ` 'Krzysztof Kozlowski'
[not found] ` <CGME20220118150112epcas5p4b63030d9bf136b4a91468b0d02e75cae@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 15/16] arm64: dts: fsd: Add initial pinctrl support Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:46 ` Krzysztof Kozlowski
2022-01-18 18:46 ` Krzysztof Kozlowski
[not found] ` <CGME20220118150116epcas5p415b4b658b3ca3fe5e52e11a33546b926@epcas5p4.samsung.com>
2022-01-18 14:48 ` [PATCH v2 16/16] arm64: defconfig: Enable Tesla FSD SoC Alim Akhtar
2022-01-18 14:48 ` Alim Akhtar
2022-01-18 18:47 ` Krzysztof Kozlowski
2022-01-18 18:47 ` Krzysztof Kozlowski
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