From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: guoren@linux.alibaba.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl Date: Wed, 19 Jan 2022 13:18:03 +0800 [thread overview] Message-ID: <20220119051824.17494-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/csr.c | 19 +++++++++++++++++++ target/riscv/pmp.c | 12 ++++-------- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9e7ac903b..6bc7ee780c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1497,9 +1497,23 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) +{ + /* TODO: RV128 restriction check */ + if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { + return false; + } + return true; +} + static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { + uint32_t reg_index = csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); return RISCV_EXCP_NONE; } @@ -1507,6 +1521,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) { + uint32_t reg_index = csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 54abf42583..81b61bb65c 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, { int i; uint8_t cfg_val; + int pmpcfg_nums = 2 << riscv_cpu_mxl(env); trace_pmpcfg_csr_write(env->mhartid, reg_index, val); - if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "ignoring pmpcfg write - incorrect address\n"); - return; - } - - for (i = 0; i < sizeof(target_ulong); i++) { + for (i = 0; i < pmpcfg_nums; i++) { cfg_val = (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } @@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) int i; target_ulong cfg_val = 0; target_ulong val = 0; + int pmpcfg_nums = 2 << riscv_cpu_mxl(env); - for (i = 0; i < sizeof(target_ulong); i++) { + for (i = 0; i < pmpcfg_nums; i++) { val = pmp_read_cfg(env, (reg_index * 4) + i); cfg_val |= (val << (i * 8)); } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl Date: Wed, 19 Jan 2022 13:18:03 +0800 [thread overview] Message-ID: <20220119051824.17494-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/csr.c | 19 +++++++++++++++++++ target/riscv/pmp.c | 12 ++++-------- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a9e7ac903b..6bc7ee780c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1497,9 +1497,23 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) +{ + /* TODO: RV128 restriction check */ + if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { + return false; + } + return true; +} + static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { + uint32_t reg_index = csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); return RISCV_EXCP_NONE; } @@ -1507,6 +1521,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) { + uint32_t reg_index = csrno - CSR_PMPCFG0; + + if (!check_pmp_reg_index(env, reg_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 54abf42583..81b61bb65c 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, { int i; uint8_t cfg_val; + int pmpcfg_nums = 2 << riscv_cpu_mxl(env); trace_pmpcfg_csr_write(env->mhartid, reg_index, val); - if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "ignoring pmpcfg write - incorrect address\n"); - return; - } - - for (i = 0; i < sizeof(target_ulong); i++) { + for (i = 0; i < pmpcfg_nums; i++) { cfg_val = (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } @@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) int i; target_ulong cfg_val = 0; target_ulong val = 0; + int pmpcfg_nums = 2 << riscv_cpu_mxl(env); - for (i = 0; i < sizeof(target_ulong); i++) { + for (i = 0; i < pmpcfg_nums; i++) { val = pmp_read_cfg(env, (reg_index * 4) + i); cfg_val |= (val << (i * 8)); } -- 2.25.1
next prev parent reply other threads:[~2022-01-19 5:23 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-19 5:18 [PATCH v7 00/22] Support UXL filed in xstatus LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei [this message] 2022-01-19 5:18 ` [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 05/22] target/riscv: Create xl field in env LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 11/22] target/riscv: Create current pm fields in env LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 21/22] target/riscv: Enable uxl field write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-20 0:35 ` Alistair Francis 2022-01-20 0:35 ` Alistair Francis 2022-01-20 2:12 ` LIU Zhiwei 2022-01-20 2:12 ` LIU Zhiwei 2022-01-20 3:29 ` Alistair Francis 2022-01-20 3:29 ` Alistair Francis 2022-01-20 5:15 ` LIU Zhiwei 2022-01-20 5:15 ` LIU Zhiwei 2022-01-20 2:33 ` LIU Zhiwei 2022-01-20 2:33 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei
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