From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: Alistair Francis <alistair23@gmail.com> Cc: guoren@linux.alibaba.com, "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: [PATCH v7 21/22] target/riscv: Enable uxl field write Date: Thu, 20 Jan 2022 10:12:41 +0800 [thread overview] Message-ID: <508b3d54-0641-cab2-c153-8f2bb76c79ed@c-sky.com> (raw) In-Reply-To: <CAKmqyKP=NNEVDDGrbSEeWLfLyX_+=Ao0yWJ9RtyazyycGHM3+w@mail.gmail.com> On 2022/1/20 上午8:35, Alistair Francis wrote: > On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> >> --- >> target/riscv/csr.c | 17 ++++++++++++----- >> 1 file changed, 12 insertions(+), 5 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index b11d92b51b..90f78eca65 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, >> { >> uint64_t mstatus = env->mstatus; >> uint64_t mask = 0; >> + RISCVMXL xl = riscv_cpu_mxl(env); >> >> /* flush tlb on mstatus fields that affect VM */ >> if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | >> @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, >> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | >> MSTATUS_TW | MSTATUS_VS; >> >> - if (riscv_cpu_mxl(env) != MXL_RV32) { >> + if (xl != MXL_RV32) { >> /* >> * RV32: MPV and GVA are not in mstatus. The current plan is to >> * add them to mstatush. For now, we just don't support it. >> */ >> mask |= MSTATUS_MPV | MSTATUS_GVA; >> + if ((val & MSTATUS64_UXL) != 0) { >> + mask |= MSTATUS64_UXL; >> + } >> } >> >> mstatus = (mstatus & ~mask) | (val & mask); >> >> - RISCVMXL xl = riscv_cpu_mxl(env); >> if (xl > MXL_RV32) { >> - /* SXL and UXL fields are for now read only */ >> + /* SXL field is for now read only */ >> mstatus = set_field(mstatus, MSTATUS64_SXL, xl); >> - mstatus = set_field(mstatus, MSTATUS64_UXL, xl); > This change causes: > > ERROR:../target/riscv/translate.c:295:get_gpr: code should not be reached > > to assert when running an Xvisor (Hypervisor extension) guest on the > 64-bit virt machine. Hi Alistair, I am almost sure that there is an UXL field write error in Xvisor. I guess there is an write_sstatus instruction that writes a 0 to SSTATUS64_UXL. We can fix it on Xvisor. But before that, we should also give more strict constraints on SSTATUS64_UXL write. + if ((val & SSTATUS64_UXL) != 0) { + mask |= SSTATUS64_UXL; + } - mask |= SSTATUS64_UXL; I will send v8 patch set later for you to test later. Thanks, Zhiwei > Alistair
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: Alistair Francis <alistair23@gmail.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, guoren@linux.alibaba.com, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: [PATCH v7 21/22] target/riscv: Enable uxl field write Date: Thu, 20 Jan 2022 10:12:41 +0800 [thread overview] Message-ID: <508b3d54-0641-cab2-c153-8f2bb76c79ed@c-sky.com> (raw) In-Reply-To: <CAKmqyKP=NNEVDDGrbSEeWLfLyX_+=Ao0yWJ9RtyazyycGHM3+w@mail.gmail.com> On 2022/1/20 上午8:35, Alistair Francis wrote: > On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> >> --- >> target/riscv/csr.c | 17 ++++++++++++----- >> 1 file changed, 12 insertions(+), 5 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index b11d92b51b..90f78eca65 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, >> { >> uint64_t mstatus = env->mstatus; >> uint64_t mask = 0; >> + RISCVMXL xl = riscv_cpu_mxl(env); >> >> /* flush tlb on mstatus fields that affect VM */ >> if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | >> @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, >> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | >> MSTATUS_TW | MSTATUS_VS; >> >> - if (riscv_cpu_mxl(env) != MXL_RV32) { >> + if (xl != MXL_RV32) { >> /* >> * RV32: MPV and GVA are not in mstatus. The current plan is to >> * add them to mstatush. For now, we just don't support it. >> */ >> mask |= MSTATUS_MPV | MSTATUS_GVA; >> + if ((val & MSTATUS64_UXL) != 0) { >> + mask |= MSTATUS64_UXL; >> + } >> } >> >> mstatus = (mstatus & ~mask) | (val & mask); >> >> - RISCVMXL xl = riscv_cpu_mxl(env); >> if (xl > MXL_RV32) { >> - /* SXL and UXL fields are for now read only */ >> + /* SXL field is for now read only */ >> mstatus = set_field(mstatus, MSTATUS64_SXL, xl); >> - mstatus = set_field(mstatus, MSTATUS64_UXL, xl); > This change causes: > > ERROR:../target/riscv/translate.c:295:get_gpr: code should not be reached > > to assert when running an Xvisor (Hypervisor extension) guest on the > 64-bit virt machine. Hi Alistair, I am almost sure that there is an UXL field write error in Xvisor. I guess there is an write_sstatus instruction that writes a 0 to SSTATUS64_UXL. We can fix it on Xvisor. But before that, we should also give more strict constraints on SSTATUS64_UXL write. + if ((val & SSTATUS64_UXL) != 0) { + mask |= SSTATUS64_UXL; + } - mask |= SSTATUS64_UXL; I will send v8 patch set later for you to test later. Thanks, Zhiwei > Alistair
next prev parent reply other threads:[~2022-01-20 2:15 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-19 5:18 [PATCH v7 00/22] Support UXL filed in xstatus LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 05/22] target/riscv: Create xl field in env LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 11/22] target/riscv: Create current pm fields in env LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 21/22] target/riscv: Enable uxl field write LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei 2022-01-20 0:35 ` Alistair Francis 2022-01-20 0:35 ` Alistair Francis 2022-01-20 2:12 ` LIU Zhiwei [this message] 2022-01-20 2:12 ` LIU Zhiwei 2022-01-20 3:29 ` Alistair Francis 2022-01-20 3:29 ` Alistair Francis 2022-01-20 5:15 ` LIU Zhiwei 2022-01-20 5:15 ` LIU Zhiwei 2022-01-20 2:33 ` LIU Zhiwei 2022-01-20 2:33 ` LIU Zhiwei 2022-01-19 5:18 ` [PATCH v7 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei 2022-01-19 5:18 ` LIU Zhiwei
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