From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>,
Robin Murphy <robin.murphy@arm.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Subject: [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional
Date: Wed, 27 Apr 2022 12:25:18 +0100 [thread overview]
Message-ID: <20220427112528.4097815-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20220427112528.4097815-1-andre.przywara@arm.com>
The Page Request Interface (PRI) is an optional PCIe feature. As such, a
SMMU would not need to handle it if the PCIe host bridge or the SMMU
itself do not implement it. Also an SMMU could be connected to a platform
device, without any PRI functionality whatsoever.
In all cases there would be no SMMU PRI queue interrupt to be wired up
to an interrupt controller.
Relax the binding to allow specifying three interrupts, omitting the PRI
IRQ. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we
would need to sacrifice the command queue sync interrupt as well, which
might not be desired.
The Linux driver does not care about any order at all, just picks IRQs
based on their names, and treats all (wired) IRQs as optional.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/iommu/arm,smmu-v3.yaml | 21 ++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index e87bfbcc69135..6b3111f1f06ce 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -37,12 +37,23 @@ properties:
hardware supports just a single, combined interrupt line.
If provided, then the combined interrupt will be used in preference to
any others.
- - minItems: 2
+ - minItems: 1
items:
- - const: eventq # Event Queue not empty
- - const: gerror # Global Error activated
- - const: priq # PRI Queue not empty
- - const: cmdq-sync # CMD_SYNC complete
+ - enum:
+ - eventq # Event Queue not empty
+ - gerror # Global Error activated
+ - cmdq-sync # CMD_SYNC complete
+ - priq # PRI Queue not empty
+ - enum:
+ - gerror
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
'#iommu-cells':
const: 1
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: devicetree@vger.kernel.org, Will Deacon <will@kernel.org>,
Liviu Dudau <liviu.dudau@arm.com>,
iommu@lists.linux-foundation.org,
Robin Murphy <robin.murphy@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional
Date: Wed, 27 Apr 2022 12:25:18 +0100 [thread overview]
Message-ID: <20220427112528.4097815-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20220427112528.4097815-1-andre.przywara@arm.com>
The Page Request Interface (PRI) is an optional PCIe feature. As such, a
SMMU would not need to handle it if the PCIe host bridge or the SMMU
itself do not implement it. Also an SMMU could be connected to a platform
device, without any PRI functionality whatsoever.
In all cases there would be no SMMU PRI queue interrupt to be wired up
to an interrupt controller.
Relax the binding to allow specifying three interrupts, omitting the PRI
IRQ. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we
would need to sacrifice the command queue sync interrupt as well, which
might not be desired.
The Linux driver does not care about any order at all, just picks IRQs
based on their names, and treats all (wired) IRQs as optional.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/iommu/arm,smmu-v3.yaml | 21 ++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index e87bfbcc69135..6b3111f1f06ce 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -37,12 +37,23 @@ properties:
hardware supports just a single, combined interrupt line.
If provided, then the combined interrupt will be used in preference to
any others.
- - minItems: 2
+ - minItems: 1
items:
- - const: eventq # Event Queue not empty
- - const: gerror # Global Error activated
- - const: priq # PRI Queue not empty
- - const: cmdq-sync # CMD_SYNC complete
+ - enum:
+ - eventq # Event Queue not empty
+ - gerror # Global Error activated
+ - cmdq-sync # CMD_SYNC complete
+ - priq # PRI Queue not empty
+ - enum:
+ - gerror
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
'#iommu-cells':
const: 1
--
2.25.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>,
Robin Murphy <robin.murphy@arm.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Subject: [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional
Date: Wed, 27 Apr 2022 12:25:18 +0100 [thread overview]
Message-ID: <20220427112528.4097815-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20220427112528.4097815-1-andre.przywara@arm.com>
The Page Request Interface (PRI) is an optional PCIe feature. As such, a
SMMU would not need to handle it if the PCIe host bridge or the SMMU
itself do not implement it. Also an SMMU could be connected to a platform
device, without any PRI functionality whatsoever.
In all cases there would be no SMMU PRI queue interrupt to be wired up
to an interrupt controller.
Relax the binding to allow specifying three interrupts, omitting the PRI
IRQ. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we
would need to sacrifice the command queue sync interrupt as well, which
might not be desired.
The Linux driver does not care about any order at all, just picks IRQs
based on their names, and treats all (wired) IRQs as optional.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/iommu/arm,smmu-v3.yaml | 21 ++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index e87bfbcc69135..6b3111f1f06ce 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -37,12 +37,23 @@ properties:
hardware supports just a single, combined interrupt line.
If provided, then the combined interrupt will be used in preference to
any others.
- - minItems: 2
+ - minItems: 1
items:
- - const: eventq # Event Queue not empty
- - const: gerror # Global Error activated
- - const: priq # PRI Queue not empty
- - const: cmdq-sync # CMD_SYNC complete
+ - enum:
+ - eventq # Event Queue not empty
+ - gerror # Global Error activated
+ - cmdq-sync # CMD_SYNC complete
+ - priq # PRI Queue not empty
+ - enum:
+ - gerror
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
+ - enum:
+ - cmdq-sync
+ - priq
'#iommu-cells':
const: 1
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-27 11:26 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-27 11:25 [PATCH 00/11] dt-bindings: convert various Arm Ltd. IP to DT schema Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara [this message]
2022-04-27 11:25 ` [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 12:04 ` Robin Murphy
2022-04-27 12:04 ` Robin Murphy
2022-04-27 12:04 ` Robin Murphy
2022-04-28 6:56 ` Krzysztof Kozlowski
2022-04-28 6:56 ` Krzysztof Kozlowski
2022-04-28 6:56 ` Krzysztof Kozlowski
2022-04-28 9:23 ` Robin Murphy
2022-04-28 9:23 ` Robin Murphy
2022-04-28 9:23 ` Robin Murphy
2022-04-28 9:25 ` Krzysztof Kozlowski
2022-04-28 9:25 ` Krzysztof Kozlowski
2022-04-28 9:25 ` Krzysztof Kozlowski
2022-05-06 15:19 ` Andre Przywara
2022-05-06 15:19 ` Andre Przywara
2022-05-06 15:19 ` Andre Przywara
2022-04-27 11:25 ` [PATCH 02/11] dt-bindings: arm: spe-pmu: convert to DT schema Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-28 6:57 ` Krzysztof Kozlowski
2022-04-28 6:57 ` Krzysztof Kozlowski
2022-04-27 11:25 ` [PATCH 03/11] dt-bindings: arm: sp810: " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-28 7:01 ` Krzysztof Kozlowski
2022-04-28 7:01 ` Krzysztof Kozlowski
2022-04-27 11:25 ` [PATCH 04/11] dt-bindings: sound: add Arm PL041 AACI " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:41 ` Mark Brown
2022-04-27 11:41 ` Mark Brown
2022-04-27 11:41 ` Mark Brown
2022-04-27 13:33 ` Andre Przywara
2022-04-27 13:33 ` Andre Przywara
2022-04-27 13:33 ` Andre Przywara
2022-04-27 13:39 ` Mark Brown
2022-04-27 13:39 ` Mark Brown
2022-04-27 13:39 ` Mark Brown
2022-04-27 13:32 ` Mark Brown
2022-04-27 13:32 ` Mark Brown
2022-04-27 13:32 ` Mark Brown
2022-04-27 13:52 ` Andre Przywara
2022-04-27 13:52 ` Andre Przywara
2022-04-27 13:52 ` Andre Przywara
2022-04-27 14:11 ` Mark Brown
2022-04-27 14:11 ` Mark Brown
2022-04-27 14:11 ` Mark Brown
2022-04-28 7:06 ` Krzysztof Kozlowski
2022-04-28 7:06 ` Krzysztof Kozlowski
2022-04-28 7:06 ` Krzysztof Kozlowski
2022-04-27 11:25 ` [PATCH 05/11] dt-bindings: serio: add Arm PL050 " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-28 7:07 ` Krzysztof Kozlowski
2022-04-28 7:07 ` Krzysztof Kozlowski
2022-04-28 17:27 ` Andre Przywara
2022-04-28 17:27 ` Andre Przywara
2022-04-29 6:29 ` Krzysztof Kozlowski
2022-04-29 6:29 ` Krzysztof Kozlowski
2022-04-29 6:35 ` Krzysztof Kozlowski
2022-04-29 6:35 ` Krzysztof Kozlowski
2022-04-29 10:06 ` Andre Przywara
2022-04-29 10:06 ` Andre Przywara
2022-04-27 11:25 ` [PATCH 06/11] dt-bindings: arm: convert vexpress-sysregs to " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 19:33 ` Rob Herring
2022-04-27 19:33 ` Rob Herring
2022-04-27 11:25 ` [PATCH 07/11] dt-bindings: arm: convert vexpress-config " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 19:37 ` Rob Herring
2022-04-27 19:37 ` Rob Herring
2022-04-27 11:25 ` [PATCH 08/11] dt-bindings: display: convert PL110/PL111 " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` [PATCH 09/11] dt-bindings: display: convert Arm HDLCD " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 19:39 ` Rob Herring
2022-04-27 19:39 ` Rob Herring
2022-04-27 19:39 ` Rob Herring
2022-04-27 11:25 ` [PATCH 10/11] dt-bindings: display: convert Arm Mali-DP " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 19:39 ` Rob Herring
2022-04-27 19:39 ` Rob Herring
2022-04-27 19:39 ` Rob Herring
2022-04-27 11:25 ` [PATCH 11/11] dt-bindings: display: convert Arm Komeda " Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 11:25 ` Andre Przywara
2022-04-27 19:29 ` [PATCH 00/11] dt-bindings: convert various Arm Ltd. IP " Rob Herring
2022-04-27 19:29 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220427112528.4097815-2-andre.przywara@arm.com \
--to=andre.przywara@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=iommu@lists.linux-foundation.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=liviu.dudau@arm.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.