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From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate
Date: Mon, 2 May 2022 18:58:52 -0400	[thread overview]
Message-ID: <20220502225852.GP384@intel.com> (raw)
In-Reply-To: <20220502163417.2635462-11-matthew.d.roper@intel.com>

On Mon, May 02, 2022 at 09:34:16AM -0700, Matt Roper wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> As we have more copy engines now, mask all of them from aux table
> invalidate.
> 
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 0de17b568b41..f262aed94ef3 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -275,7 +275,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
>  		if (!HAS_FLAT_CCS(rq->engine->i915) &&
>  		    (rq->engine->class == VIDEO_DECODE_CLASS ||
>  		     rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
> -			aux_inv = rq->engine->mask & ~BIT(BCS0);
> +			aux_inv = rq->engine->mask & ~GENMASK(BCS8, BCS0);
If we had defined I915_MAX_BCS earlier.
We use ~GENMASK(BCS0 + I915_MAX_BCS - 1, BCS0), so we don't need to
change this with the number of instances.

Otherwise looks good to me.

Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>  			if (aux_inv)
>  				cmd += 4;
>  		}
> -- 
> 2.35.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate
Date: Mon, 2 May 2022 18:58:52 -0400	[thread overview]
Message-ID: <20220502225852.GP384@intel.com> (raw)
In-Reply-To: <20220502163417.2635462-11-matthew.d.roper@intel.com>

On Mon, May 02, 2022 at 09:34:16AM -0700, Matt Roper wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> As we have more copy engines now, mask all of them from aux table
> invalidate.
> 
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 0de17b568b41..f262aed94ef3 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -275,7 +275,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
>  		if (!HAS_FLAT_CCS(rq->engine->i915) &&
>  		    (rq->engine->class == VIDEO_DECODE_CLASS ||
>  		     rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
> -			aux_inv = rq->engine->mask & ~BIT(BCS0);
> +			aux_inv = rq->engine->mask & ~GENMASK(BCS8, BCS0);
If we had defined I915_MAX_BCS earlier.
We use ~GENMASK(BCS0 + I915_MAX_BCS - 1, BCS0), so we don't need to
change this with the number of instances.

Otherwise looks good to me.

Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>  			if (aux_inv)
>  				cmd += 4;
>  		}
> -- 
> 2.35.1
> 

  parent reply	other threads:[~2022-05-02 22:58 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-02 16:34 [PATCH 00/11] i915: Introduce Ponte Vecchio Matt Roper
2022-05-02 16:34 ` [Intel-gfx] " Matt Roper
2022-05-02 16:34 ` [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 20:44   ` Lucas De Marchi
2022-05-02 20:44     ` [Intel-gfx] " Lucas De Marchi
2022-05-02 16:34 ` [PATCH 02/11] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 22:33   ` Summers, Stuart
2022-05-02 22:33     ` [Intel-gfx] " Summers, Stuart
2022-05-05  0:34     ` Matt Roper
2022-05-05  0:34       ` Matt Roper
2022-05-02 16:34 ` [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:50   ` Matt Roper
2022-05-02 16:50     ` [Intel-gfx] " Matt Roper
2022-05-02 18:39     ` Lucas De Marchi
2022-05-02 18:50       ` Matt Roper
2022-05-02 19:27         ` Lucas De Marchi
2022-05-02 19:42           ` Matt Roper
2022-05-02 21:03   ` Lucas De Marchi
2022-05-02 21:03     ` [Intel-gfx] " Lucas De Marchi
2022-05-02 21:14     ` Matt Roper
2022-05-02 21:14       ` [Intel-gfx] " Matt Roper
2022-05-03  6:22       ` Lucas De Marchi
2022-05-03  6:22         ` [Intel-gfx] " Lucas De Marchi
2022-05-02 16:34 ` [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:55   ` Rodrigo Vivi
2022-05-02 16:55     ` [Intel-gfx] " Rodrigo Vivi
2022-05-02 16:34 ` [PATCH 05/11] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:34 ` [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:46   ` Souza, Jose
2022-05-02 18:46     ` [Intel-gfx] " Souza, Jose
2022-05-03  8:25   ` Tvrtko Ursulin
2022-05-02 16:34 ` [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:45   ` Souza, Jose
2022-05-03  8:05   ` Tvrtko Ursulin
2022-05-03  8:05     ` Tvrtko Ursulin
2022-05-05 20:59     ` Matt Roper
2022-05-05 20:59       ` Matt Roper
2022-05-06  7:21       ` Tvrtko Ursulin
2022-05-06  7:21         ` Tvrtko Ursulin
2022-05-06 14:29         ` Matt Roper
2022-05-06 14:29           ` Matt Roper
2022-05-02 16:34 ` [PATCH 08/11] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 22:23   ` Summers, Stuart
2022-05-02 22:23     ` [Intel-gfx] " Summers, Stuart
2022-05-02 16:34 ` [PATCH 09/11] drm/i915/pvc: Reset " Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:44   ` Souza, Jose
2022-05-02 22:23   ` Summers, Stuart
2022-05-02 16:34 ` [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:40   ` Souza, Jose
2022-05-02 22:58   ` Kumar Valsan, Prathap [this message]
2022-05-02 22:58     ` Kumar Valsan, Prathap
2022-05-02 16:34 ` [PATCH 11/11] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:48   ` Souza, Jose
2022-05-02 18:48     ` [Intel-gfx] " Souza, Jose
2022-05-03  8:19   ` Tvrtko Ursulin
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio Patchwork
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-02 22:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-03 17:32   ` Matt Roper
2022-05-04 17:03     ` Vudum, Lakshminarayana
2022-05-03  8:21 ` [Intel-gfx] [PATCH 00/11] " Tvrtko Ursulin
2022-05-03 14:56   ` Matt Roper
2022-05-03 15:01     ` Tvrtko Ursulin
2022-05-04 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2022-05-04 16:43 ` Patchwork

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