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From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Harrison, John C" <john.c.harrison@intel.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
Date: Mon, 2 May 2022 18:46:36 +0000	[thread overview]
Message-ID: <b308861d15d0fe885a236a38ca097baf5de50ba4.camel@intel.com> (raw)
In-Reply-To: <20220502163417.2635462-7-matthew.d.roper@intel.com>

On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> PVC adds extra blitter engines (in the following patch). The reset
> selftest has a local array on the stack which is sized by the number
> of engines. The increase pushes the size of this array to the point
> where it trips the 'stack too large' compile warning. This patch takes
> the allocation of the stack and makes it dynamic instead.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 83ff4c2e57c5..3b9d82276db2 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -979,6 +979,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  	enum intel_engine_id id, tmp;
>  	struct hang h;
>  	int err = 0;
> +	struct active_engine *threads;
>  
>  	/* Check that issuing a reset on one engine does not interfere
>  	 * with any other engine.
> @@ -996,8 +997,11 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			h.ctx->sched.priority = 1024;
>  	}
>  
> +	threads = kzalloc(sizeof(*threads) * I915_NUM_ENGINES, GFP_KERNEL);
> +	if (!threads)
> +		return -ENOMEM;
> +
>  	for_each_engine(engine, gt, id) {
> -		struct active_engine threads[I915_NUM_ENGINES] = {};
>  		unsigned long device = i915_reset_count(global);
>  		unsigned long count = 0, reported;
>  		bool using_guc = intel_engine_uses_guc(engine);
> @@ -1016,7 +1020,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			break;
>  		}
>  
> -		memset(threads, 0, sizeof(threads));
> +		memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
>  		for_each_engine(other, gt, tmp) {
>  			struct task_struct *tsk;
>  
> @@ -1236,6 +1240,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			break;
>  		}
>  	}
> +	kfree(threads);
>  
>  	if (intel_gt_is_wedged(gt))
>  		err = -EIO;


WARNING: multiple messages have this Message-ID (diff)
From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
Date: Mon, 2 May 2022 18:46:36 +0000	[thread overview]
Message-ID: <b308861d15d0fe885a236a38ca097baf5de50ba4.camel@intel.com> (raw)
In-Reply-To: <20220502163417.2635462-7-matthew.d.roper@intel.com>

On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> PVC adds extra blitter engines (in the following patch). The reset
> selftest has a local array on the stack which is sized by the number
> of engines. The increase pushes the size of this array to the point
> where it trips the 'stack too large' compile warning. This patch takes
> the allocation of the stack and makes it dynamic instead.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 83ff4c2e57c5..3b9d82276db2 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -979,6 +979,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  	enum intel_engine_id id, tmp;
>  	struct hang h;
>  	int err = 0;
> +	struct active_engine *threads;
>  
>  	/* Check that issuing a reset on one engine does not interfere
>  	 * with any other engine.
> @@ -996,8 +997,11 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			h.ctx->sched.priority = 1024;
>  	}
>  
> +	threads = kzalloc(sizeof(*threads) * I915_NUM_ENGINES, GFP_KERNEL);
> +	if (!threads)
> +		return -ENOMEM;
> +
>  	for_each_engine(engine, gt, id) {
> -		struct active_engine threads[I915_NUM_ENGINES] = {};
>  		unsigned long device = i915_reset_count(global);
>  		unsigned long count = 0, reported;
>  		bool using_guc = intel_engine_uses_guc(engine);
> @@ -1016,7 +1020,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			break;
>  		}
>  
> -		memset(threads, 0, sizeof(threads));
> +		memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
>  		for_each_engine(other, gt, tmp) {
>  			struct task_struct *tsk;
>  
> @@ -1236,6 +1240,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
>  			break;
>  		}
>  	}
> +	kfree(threads);
>  
>  	if (intel_gt_is_wedged(gt))
>  		err = -EIO;


  reply	other threads:[~2022-05-02 18:46 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-02 16:34 [PATCH 00/11] i915: Introduce Ponte Vecchio Matt Roper
2022-05-02 16:34 ` [Intel-gfx] " Matt Roper
2022-05-02 16:34 ` [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 20:44   ` Lucas De Marchi
2022-05-02 20:44     ` [Intel-gfx] " Lucas De Marchi
2022-05-02 16:34 ` [PATCH 02/11] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 22:33   ` Summers, Stuart
2022-05-02 22:33     ` [Intel-gfx] " Summers, Stuart
2022-05-05  0:34     ` Matt Roper
2022-05-05  0:34       ` Matt Roper
2022-05-02 16:34 ` [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:50   ` Matt Roper
2022-05-02 16:50     ` [Intel-gfx] " Matt Roper
2022-05-02 18:39     ` Lucas De Marchi
2022-05-02 18:50       ` Matt Roper
2022-05-02 19:27         ` Lucas De Marchi
2022-05-02 19:42           ` Matt Roper
2022-05-02 21:03   ` Lucas De Marchi
2022-05-02 21:03     ` [Intel-gfx] " Lucas De Marchi
2022-05-02 21:14     ` Matt Roper
2022-05-02 21:14       ` [Intel-gfx] " Matt Roper
2022-05-03  6:22       ` Lucas De Marchi
2022-05-03  6:22         ` [Intel-gfx] " Lucas De Marchi
2022-05-02 16:34 ` [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:55   ` Rodrigo Vivi
2022-05-02 16:55     ` [Intel-gfx] " Rodrigo Vivi
2022-05-02 16:34 ` [PATCH 05/11] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 16:34 ` [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:46   ` Souza, Jose [this message]
2022-05-02 18:46     ` Souza, Jose
2022-05-03  8:25   ` Tvrtko Ursulin
2022-05-02 16:34 ` [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:45   ` Souza, Jose
2022-05-03  8:05   ` Tvrtko Ursulin
2022-05-03  8:05     ` Tvrtko Ursulin
2022-05-05 20:59     ` Matt Roper
2022-05-05 20:59       ` Matt Roper
2022-05-06  7:21       ` Tvrtko Ursulin
2022-05-06  7:21         ` Tvrtko Ursulin
2022-05-06 14:29         ` Matt Roper
2022-05-06 14:29           ` Matt Roper
2022-05-02 16:34 ` [PATCH 08/11] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 22:23   ` Summers, Stuart
2022-05-02 22:23     ` [Intel-gfx] " Summers, Stuart
2022-05-02 16:34 ` [PATCH 09/11] drm/i915/pvc: Reset " Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:44   ` Souza, Jose
2022-05-02 22:23   ` Summers, Stuart
2022-05-02 16:34 ` [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:40   ` Souza, Jose
2022-05-02 22:58   ` Kumar Valsan, Prathap
2022-05-02 22:58     ` Kumar Valsan, Prathap
2022-05-02 16:34 ` [PATCH 11/11] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-02 16:34   ` [Intel-gfx] " Matt Roper
2022-05-02 18:48   ` Souza, Jose
2022-05-02 18:48     ` [Intel-gfx] " Souza, Jose
2022-05-03  8:19   ` Tvrtko Ursulin
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio Patchwork
2022-05-02 16:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-02 17:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-02 22:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-03 17:32   ` Matt Roper
2022-05-04 17:03     ` Vudum, Lakshminarayana
2022-05-03  8:21 ` [Intel-gfx] [PATCH 00/11] " Tvrtko Ursulin
2022-05-03 14:56   ` Matt Roper
2022-05-03 15:01     ` Tvrtko Ursulin
2022-05-04 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2022-05-04 16:43 ` Patchwork

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