From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org,
~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
kernel@collabora.com,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
Date: Fri, 13 May 2022 19:16:17 +0200 [thread overview]
Message-ID: <20220513171617.504430-8-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com>
This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
<0 0x10226000 0 0x2000>;
};
+ cci: cci@10390000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x10390000 0 0x1000>;
+ ranges = <0 0 0x10390000 0x10000>;
+
+ cci_control0: slave-if@1000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace-lite";
+ reg = <0x1000 0x1000>;
+ };
+
+ cci_control1: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
--
2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org,
~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
kernel@collabora.com,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
Date: Fri, 13 May 2022 19:16:17 +0200 [thread overview]
Message-ID: <20220513171617.504430-8-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com>
This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
<0 0x10226000 0 0x2000>;
};
+ cci: cci@10390000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x10390000 0 0x1000>;
+ ranges = <0 0 0x10390000 0x10000>;
+
+ cci_control0: slave-if@1000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace-lite";
+ reg = <0x1000 0x1000>;
+ };
+
+ cci_control1: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
--
2.35.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org,
~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
kernel@collabora.com,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
Date: Fri, 13 May 2022 19:16:17 +0200 [thread overview]
Message-ID: <20220513171617.504430-8-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com>
This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
+ cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
+ cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
<0 0x10226000 0 0x2000>;
};
+ cci: cci@10390000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x10390000 0 0x1000>;
+ ranges = <0 0 0x10390000 0x10000>;
+
+ cci_control0: slave-if@1000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace-lite";
+ reg = <0x1000 0x1000>;
+ };
+
+ cci_control1: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-13 17:16 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-13 17:16 [PATCH 0/7] MediaTek Helio X10 MT6795 - Devicetree, part 1 AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` [PATCH 1/7] arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` [PATCH 2/7] arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` [PATCH 3/7] arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` [PATCH 4/7] arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-16 7:10 ` Krzysztof Kozlowski
2022-05-16 7:10 ` Krzysztof Kozlowski
2022-05-16 7:10 ` Krzysztof Kozlowski
2022-05-16 8:51 ` AngeloGioacchino Del Regno
2022-05-16 8:51 ` AngeloGioacchino Del Regno
2022-05-16 8:51 ` AngeloGioacchino Del Regno
2022-05-16 14:51 ` Krzysztof Kozlowski
2022-05-16 14:51 ` Krzysztof Kozlowski
2022-05-16 14:51 ` Krzysztof Kozlowski
2022-05-17 8:14 ` AngeloGioacchino Del Regno
2022-05-17 8:14 ` AngeloGioacchino Del Regno
2022-05-17 8:14 ` AngeloGioacchino Del Regno
2022-05-17 8:18 ` Krzysztof Kozlowski
2022-05-17 8:18 ` Krzysztof Kozlowski
2022-05-17 8:18 ` Krzysztof Kozlowski
2022-05-13 17:16 ` [PATCH 6/7] arm64: dts: mediatek: mt6795: Add general purpose timer node AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno [this message]
2022-05-13 17:16 ` [PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs AngeloGioacchino Del Regno
2022-05-13 17:16 ` AngeloGioacchino Del Regno
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